Abstract: A display may have a pixel array such as a liquid crystal pixel array. The pixel array may be illuminated with backlight illumination from a direct-lit backlight unit. The backlight unit may include an array of light-emitting diodes (LEDs) on a printed circuit board. The display may have a notch to accommodate an input-output component. Reflective layers may be included in the notch. The backlight may include a color conversion layer with a property that varies as a function of position. The light-emitting diodes may be covered by a slab of encapsulant with recesses in an upper surface.

Abstract: A display may have a pixel array such as a liquid crystal pixel array. The pixel array may be illuminated with backlight illumination from a direct-lit backlight unit. The backlight unit may include an array of light-emitting diodes (LEDs) on a printed circuit board. The display may have a notch to accommodate an input-output component. Reflective layers may be included in the notch. The backlight may include a color conversion layer with a property that varies as a function of position. The light-emitting diodes may be covered by a slab of encapsulant with recesses in an upper surface.

Abstract: A display may have a pixel array such as a liquid crystal pixel array. The pixel array may be illuminated with backlight illumination from a direct-lit backlight unit. The backlight unit may include an array of light-emitting diodes (LEDs) on a printed circuit board. The display may have a notch to accommodate an input-output component. Reflective layers may be included in the notch. The backlight may include a color conversion layer with a property that varies as a function of position. The light-emitting diodes may be covered by a slab of encapsulant with recesses in an upper surface.

Abstract: The invention is a system for monitoring and controlling tissue ablation. The system includes a controller configured to selectively control energy emission from an electrode array of an ablation device based on ablation feedback received during an ablation procedure with the ablation device. The controller is configured to receive feedback data from one or more sensors during the ablation procedure, the feedback data comprising one or more measurements associated with at least one of operation of the electrode array of the ablation device and tissue adjacent to the electrode array. The controller is further configured to generate an ablation pattern for controlling energy emission from the electrode array of the ablation device in response to the received feedback data.

Abstract: The invention is a system for monitoring and controlling tissue ablation. The system includes a controller configured to selectively control energy emission from an electrode array of an ablation device based on ablation feedback received during an ablation procedure with the ablation device. The controller is configured to receive feedback data from one or more sensors during the ablation procedure, the feedback data comprising one or more measurements associated with at least one of operation of the electrode array of the ablation device and tissue adjacent to the electrode array. The controller is further configured to generate an ablation pattern for controlling energy emission from the electrode array of the ablation device in response to the received feedback data.

Abstract: The invention is a system for monitoring and controlling tissue ablation. The system includes a controller configured to selectively control energy emission from an electrode array of an ablation device based on ablation feedback received during an ablation procedure with the ablation device. The controller is configured to receive feedback data from one or more sensors during the ablation procedure, the feedback data comprising one or more measurements associated with at least one of operation of the electrode array of the ablation device and tissue adjacent to the electrode array. The controller is further configured to generate an ablation pattern for controlling energy emission from the electrode array of the ablation device in response to the received feedback data.

Abstract: A multimedia cable, particularly one designed to carry digital signals in accordance with an HDMI standard, which comprises two or more concentric rings of conductor cores arranged about a central conductor core.

Abstract: Techniques a race logic analysis on an integrated circuit (IC) design are described herein. In one embodiment, all hardware description language (HDL) defined system functions and/or tasks that have one or more side-effects when invoked in a first HDL language, but not when the same HDL-defined system functions/tasks are invoked in a second HDL language are identified. For all processing blocks that invoke the HDL-defined system functions/tasks that have side-effects, one or more triggering conditions of the processing blocks and HDL languages in which the processing blocks are coded are collected. When detecting a concurrent invocation race of the HDL-defined system functions/tasks statically or dynamically, checking is performed only the processing blocks that are coded in one or more HDL languages which render the HDL-defined system functions/tasks to manifest the one or more side-effects. Other methods and apparatuses are also described.

Abstract: This invention describes a race logic audit program, RaceCheck, which is unique from the prior arts. Specifically, RaceCheck can perform both static and dynamic race logic analysis, and it works with a plurality of hardware description languages (HDL), which include but not limited to: VHDL, Verilog, SystemVerilog, and SystemC. Furthermore, RaceCheck makes use of both structural and timing information of IC designs, as well as binary-decision diagram (BDD) and automatic test pattern generation (ATPG) techniques to derive accurate race logic analysis results with few false violations. Finally, RaceCheck can detect concurrent invocation races of the $random system function, concurrent invocation races of user-defined tasks and functions, zero-delay combination loops, and RaceCheck's dynamic analysis engine uses a HDL simulation kernel to perform timing-accurate race logic analysis. All these aforementioned features are unique for the invention and have not been reported in any prior arts.

Abstract: This invention describes a multithread HDL logic simulator that is unique from the prior arts. Specifically, it can process both VHDL and Verilog languages in a single program, and it uses special concurrent algorithms to accelerate the tool's performance on multiprocessor platforms to achieve linear to super-linear scalability on multiprocessor systems. Furthermore, the invention includes a unique remote logic simulation and job scheduling capabilities.