Abstract: A three-dimensional microelectronic package for semiconductor chips includes alternating layers of wafer interconnect stacks and chip carrier modules. The wafer interconnect stacks provide electrical interconnections in the x, y, and z directions. The wafer interconnect stacks have conductive segments and interposers to provide signal path selection in the z-axis direction, and bump technology to provide high quality contacts between layers and continuity of the z-axis signal paths. Each layer of chip carrier modules includes a plurality of modules arranged in a preselected pattern. Each module comprises a chip carrier coupon which has a semiconductor chip mounted thereon, at least one annular spacer coupon provided on the carrier coupon and having an aperture aligned with the semiconductor chip and an opening which is aligned with a coolant discharge port in a coolant supply tube, and a lid. A coolant cavity is defined by the aperture in the spacer coupon(s).