Abstract: A bipolar lateral transistor is formed in a highly doped p.sup.- -type well (13) the base contained in a lightly doped n.sup.- -type well (12) the collector in a very lightly doped p.sup.-- -type substrate (11). The arrangement is such that the boundary of the collector/base depletion region is distributed so that the non-depleted base region is wide below the emitter but very narrow at the surface. This defines a narrow active base region in the lateral emitter-collector path thus ensuring that the transistor operates predominantly in its lateral rather than its vertical mode. The structure is compatible with conventional CMOS and NMOS processing techniques.

Abstract: A CMOS logic input circuit comprises two complementary transistor pairs, TR1 and TR2; TR3 and TR4 coupled in series between the supply rails. The gates of n-channel transistor TR4 and p-channel transistor TR1 are coupled to the positive and negative supply rails respectively. A switching function is performed by TR2 and TR3.The arrangement is such that the switching threshold is substantially independent of transistor characteristics.