Patents by Inventor Terence J. Magee

Terence J. Magee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Configurable high-speed memory interface subsystem
    Patent number: 7437500
    Abstract: A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The read logic IP block may be configured to communicate data from the double data rate (DDR) synchronous dynamic random access memory (SDRAM) to the memory controller. The master delay IP block may be configured to generate one or more delays for the read logic IP block. The address and control logic IP block may be configured to control the write logic IP block and the read logic IP block. The core is generally configured to couple the double data rate (DDR) synchronous dynamic random access memory (SDRAM) and the memory controller.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: October 14, 2008
    Assignee: LSI Corporation
    Inventors: Derrick Sai-Tang Butt, Cheng-Gang Kong, Terence J. Magee