Abstract: A data processing unit accesses data in a cache using a virtual address. If the data is not in the cache, the virtual address is translated by a memory management unit (MMU) into a physical address for accessing a main memory. The MMU can also access the cache, using the physical address, to retrieve page table entries held in the cache. This avoids the need for a main memory access to retrieve the page table entries, and hence speeds up the address translation operation. The physically addressed entries in the cache are tagged with a reserved context number to distinguish them from the virtually addressed data.

Abstract: A multi-processor data processing system, comprises a plurality of data processing modules. A set of interrupt lines are connected in parallel to all the processing modules. Each processing module has a priority level, and the lowest priority module is selected to act as an interrupt handler, with responsibility for handling all balanced interrupts. Whenever a processing module changes it priority, it clocks to see whether the interrupt handler is still the lowest priority module and, if not, causes the role of interrupt handler to be transferred.

Abstract: A multi-cache data storage system has a number of cache units and a main memory. The caches are addressed by a virtual address. When data is updated in one of the caches, the virtual address is translated into a physical address and sent to the main memory over a bus, along with the updated data value. Each cache continuously monitors the bus for updates from other caches and checks whether it holds a data item corresponding to the physical address. If so, the data item is updated or invalidated, so as to ensure cache coherency.