Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

Abstract: A system includes a programmable logic fabric core of an integrated circuit device and an IO interface communicatively coupled to the programmable logic fabric core. The IO interface includes multiple IO banks to implement a memory channel. Each IO bank includes a memory controller to control memory accesses of a memory device over the memory channel and multiple physical layer and IOs circuits to provide connections between the memory controller and the memory device. The respective memory controller may receive only a portion of data to be sent over the memory channel or multiple memory controllers may each receive all data to be sent over the memory channel.

Abstract: Systems or methods of the present disclosure may provide a programmable logic fabric and a memory controller communicatively coupled to the programmable logic fabric. The systems or methods also include a physical layer and IO circuit coupled to the programmable logic fabric via the memory controller and a FIFO to receive read data from a memory device coupled to the physical layer and IO circuit. Furthermore, the FIFO is closer to the memory controller than to the physical layer and IO circuit.

Abstract: A memory interface circuit includes first and second memory controller circuits that asynchronously receive requests for memory accesses to first and second storage circuits. The memory interface circuit also includes first and second clock gate circuits that disable and then reenable first and second clock signals in response to a clock enable signal. The first and the second memory controller circuits perform the memory accesses to the first and the second storage circuits synchronously in response to the first and the second clock signals that have been reenabled by the first and the second clock gate circuits.

Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

Abstract: In an apparatus relating generally to the communication of data, a first and a second receive path block are respectively coupled to receive a first and a second data stream. A clock signal source is coupled to provide at least one clock signal to each of the first and the second receive path block. A control block is coupled to receive a first output signal pair and a second output signal pair from the first and the second receive path block, respectively. The first output signal pair includes a first crossing signal and a first data signal. The second output signal pair includes a second crossing signal and a second data signal. The control block is configured to provide first and second delay adjustment signals respectively to the first and second receive path blocks, to adjust delays of the first and second data streams, respectively.

Abstract: A data interface enabling the calibration of input data comprises a first data receiver having a first plurality of input data lines coupled to receive a corresponding first plurality of data bits associated with a data bus, the first data receiver having a first control circuit enabling calibration of the first plurality of input data lines; and a second data receiver having a second plurality of input data lines coupled to receive a corresponding second plurality of data bits associated with the data bus, the second data receiver having a second control circuit enabling calibration of the second plurality of data lines. The first plurality of input data lines of the first data receiver are calibrated in parallel with the second plurality of input data lines of the second data receiver.

Abstract: The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO(First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained. A ratio is calculated for each Functional delay cell by dividing the Functional delay cells' setting into the spare delay cells' one-fourth cycle setting. These ratios reflect any process variation. Functional mode is then entered and a Master-Slave approach switched to, during which the spare delay cell repeats the training sequence continuously while the Functional delay cells delay the clocks from the RAM(Random Access Memory). Each Functional delay cell is updated at the end of each training sequence of the spare delay cell, compensating for voltage and temperature change, by dividing the ratio into the new spare delay cell one-fourth cycle setting.

Abstract: The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO (First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained. A ratio is calculated for each Functional delay cell by dividing the Functional delay cells' setting into the spare delay cells' one-fourth cycle setting. These ratios reflect any process variation. Functional mode is then entered and a Master-Slave approach switched to, during which the spare delay cell repeats the training sequence continuously while the Functional delay cells delay the clocks from the RAM (Random Access Memory). Each Functional delay cell is updated at the end of each training sequence of the spare delay cell, compensating for voltage and temperature change, by dividing the ratio into the new spare delay cell one-fourth cycle setting.

Abstract: A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The read logic IP block may be configured to communicate data from the double data rate (DDR) synchronous dynamic random access memory (SDRAM) to the memory controller. The master delay IP block may be configured to generate one or more delays for the read logic IP block. The address and control logic IP block may be configured to control the write logic IP block and the read logic IP block. The core is generally configured to couple the double data rate (DDR) synchronous dynamic random access memory (SDRAM) and the memory controller.

Abstract: A process and system is disclosed to assist work planners by assembling a work breakdown structure (WBS) and work flow for a project based on the explicit selection or deselection of outcome(s) by a work planner from a defined set of possible outcomes. The process and system ensure that the resulting project WBS and work flow is composed of the minimum set of activities required to produce the set of outcomes desired for the project. The process and system further ensure that the project's activities are organized into an activity hierarchy defined by a WBS template designated by the work planner, and that each of the project's activities is linked into an appropriate work flow, supported by appropriate instructional or descriptive content.

Abstract: An apparatus for the detection of a wearer includes a first inner layer that is adapted to reflect a portion of radar energy back toward its source. A second outer layer is disposed over the first inner layer and it provides a texture and visual appearance that is preferred. For some applications, an especially easy to spot brightly colored visual appearance is preferred for the second outer layer. For other applications, a more subdued visual appearance is preferred. For still other applications, a camouflage appearance is preferred. A space is provided intermediate the first inner layer and the second outer layer accordingly to a modification and an additional material is used to fill the space. The additional material must be substantially transparent to radar energy and it may provide additional floatation capability or additional insulating capability or both to the garment, as desired.

Abstract: An apparatus for the detection of a person afloat in the water includes a garment portion that is worn by the person. The garment portion preferably includes an inflatable vest. An actuation mechanism detects immersion in the water, preferably at a predetermined depth, and then automatically inflates the vest by puncturing or opening a first container and releasing a gas therein. A balloon is also attached to the vest and is also inflated by the gas of the first container providing the gas in the first container is a lighter-than-air type of a gas that is able to cause the balloon to rise in the air. A tether secures the balloon to the vest. If the gas in the first container is not suitable for filling the balloon, a second container is used that contains the desired lighter-than-air gas and it is also either punctured or otherwise opened by the actuation mechanism so as to inflate the balloon.

Abstract: A process and system is disclosed to assist work planners by assembling a work breakdown structure (WBS) and work flow for a project based on the explicit selection or de-selection of outcome(s) by a work planner from a defined set of possible outcomes. The process and system ensure that the resulting project WBS and work flow is composed of the minimum set of activities required to produce the set of outcomes desired for the project. The process and system further ensure that the project's activities are organized into an activity hierarchy defined by a WBS template designated by the work planner, and that each of the project's activities is linked into an appropriate work flow, supported by appropriate instructional content.