Patents by Inventor Terence Quintin Collier

Terence Quintin Collier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for inhibiting corrosion and removing contaminant from a surface during wafer dicing and composition useful therefor
    Patent number: 8580656
    Abstract: Adherence of contaminant residues or particles is suppressed, corrosion of exposed surfaces is substantially reduced or eliminated during the process of dicing a wafer by sawing. A fluoride-free aqueous composition comprising a dicarboxylic acid and/or salt thereof; a hydroxycarboxylic acid and/or salt thereof or amine group containing acid, a surfactant and deionized water is employed.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: November 12, 2013
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Terence Quintin Collier, Charles A. Lhota, David Barry Rennie, Rajkumar Ramamurthi, Madhukar Bhaskara Rao, Dnyanesh Chandrakant Tamboli
  • Process for Inhibiting Corrosion and Removing Contaminant from a Surface During Wafer Dicing and Composition Useful Therefor
    Publication number: 20100009517
    Abstract: Adherence of contaminant residues or particles is suppressed, corrosion of exposed surfaces is substantially reduced or eliminated during the process of dicing a wafer by sawing. A fluoride-free aqueous composition comprising a dicarboxylic acid and/or salt thereof; a hydroxycarboxylic acid and/or salt thereof or amine group containing acid, a surfactant and deionized water is employed.
    Type: Application
    Filed: July 8, 2009
    Publication date: January 14, 2010
    Applicant: AIR PRODUCTS AND CHEMICALS, INC.
    Inventors: Terence Quintin Collier, Charles A. Lhota, David Barry Rennie, Rajkumar Ramamurthi, Madhukar Bhaskara Rao, Dnyanesh Chandrakant Tamboli
  • Tool and fixture for measuring mechanical and electromechanical properties for IC assemblies and features
    Publication number: 20040181304
    Abstract: Disclosed are the methods and tools to reliably and accurately predict and model the strength of the individual features and structures of semiconductor components. By modifying the traditional anvil/pyramidal indentors on a hardness tester, an improved method has been created to evaluate the mechanical forces on micron and submicron devices. This tool will provide a method to predict and analyze various mechanical, electrical and electromechanical states to help improve process yield, overall reliability, and design features. The modified tool will provide both a real-time process tool as well a development tool.
    Type: Application
    Filed: December 11, 2003
    Publication date: September 16, 2004
    Inventor: Terence Quintin Collier
  • Semiconductor package method
    Publication number: 20040046236
    Abstract: Disclosed are semiconductor packages and methods incorporating the use of vias in layers of leaded and nonleaded multilayer packages. The vias provide fluid communication between layers such that bonding material flows among layers for the formation of a 3D bond. As disclosed, the layers may comprise leads, dice, bond pads, or other substantially planar semiconductor package surfaces.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 11, 2004
    Inventor: Terence Quintin Collier
  • Semiconductor package device
    Patent number: 6646332
    Abstract: Disclosed are semiconductor packages and methods incorporating the use of vias in layers of leaded and nonleaded multilayer packages. The vias provide fluid communication between layers such that bonding material flows among layers for the formation of a 3D bond. As disclosed, the layers may comprise leads, dice, bond pads, or other substantially planar semiconductor package surfaces.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: November 11, 2003
    Inventor: Terence Quintin Collier
  • Semiconductor package device and method
    Publication number: 20030137036
    Abstract: Disclosed are semiconductor packages and methods incorporating the use of vias in layers of leaded and nonleaded multilayer packages. The vias provide fluid communication between layers such that bonding material flows among layers for the formation of a 3D bond. As disclosed, the layers may comprise leads, dice, bond pads, or other substantially planar semiconductor package surfaces.
    Type: Application
    Filed: August 7, 2002
    Publication date: July 24, 2003
    Inventor: Terence Quintin Collier