Patents by Inventor Teresa B. Sapirman
Teresa B. Sapirman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Oxides with thin metallic layers as transparent ohmic contacts for p-type and n-type gallium nitride
Patent number: 9306126Abstract: Transparent conductive layers usable as ohmic contacts for III-V semiconductors with work functions between 4.1 and 4.7 eV are formed by annealing layers of transparent oxide with thin (0.1-5nm) layers of conductive metal. When the layers interdiffuse during the annealing, some of the conductive metal atoms remain free to reduce resistivity and others oxidize to reduce optical absorption. Examples of the transparent oxides include indium-tin oxide, zinc oxide, and aluminum zinc oxide with up to 5 wt % Al. Examples of the metals include aluminum and titanium. The work function of the transparent conductive layer can be tuned to match the contacted semiconductor by adjusting the ratio of metal to transparent oxide.Type: GrantFiled: July 14, 2014Date of Patent: April 5, 2016Assignee: Intermolecular, Inc.Inventors: Jianhua Hu, Heng-Kai Hsu, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman -
Patent number: 9246062Abstract: Transparent ohmic contacts to p-GaN and other high-work-function (?4.2 eV) semiconductors are fabricated from zinc stannate (e.g., ZnSnO3). ZnO and SnO2 may be sputtered from separate targets and annealed to form the zinc stannate. The Zn:Sn ratio may be tuned over the range between 1:2 and 2:1 to optimize bandgap, work function, conductivity, and transparency for the particular semiconductor and wavelength of interest. Conductivity may be improved by crystallizing the zinc stannate, by doping with up to 5 wt % Al or In, or both.Type: GrantFiled: April 23, 2014Date of Patent: January 26, 2016Assignee: Intermolecular, Inc.Inventors: Jianhua Hu, Heng Kai Hsu, Tong Ju, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
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Oxides with Thin Metallic Layers as Transparent Ohmic Contacts for P-Type and N-Type Gallium Nitride
Publication number: 20160013367Abstract: Transparent conductive layers usable as ohmic contacts for III-V semiconductors with work functions between 4.1 and 4.7 eV are formed by annealing layers of transparent oxide with thin (0.1-5 nm) layers of conductive metal. When the layers interdiffuse during the annealing, some of the conductive metal atoms remain free to reduce resistivity and others oxidize to reduce optical absorption. Examples of the transparent oxides include indium-tin oxide, zinc oxide, and aluminum zinc oxide with up to 5 wt % Al. Examples of the metals include aluminum and titanium. The work function of the transparent conductive layer can be tuned to match the contacted semiconductor by adjusting the ratio of metal to transparent oxide.Type: ApplicationFiled: July 14, 2014Publication date: January 14, 2016Inventors: Jianhua Hu, Heng-Kai Hsu, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman -
Publication number: 20150318446Abstract: A ternary transparent conductive oxide, indium zinc oxide (IZO), is formed as a thin film by co-sputtering zinc oxide with indium oxide at a deposition temperature between 25 and 200 C. Optionally, up to 1-2% Al may be added by various methods. The layers may be annealed at temperatures between 200 and 400 C. Measurements of IZO with 75-85 wt % In2O3 showed low resistivity and low visible absorbance, both of which were thermally stable up to 400 C.Type: ApplicationFiled: April 30, 2014Publication date: November 5, 2015Applicant: Intermolecular, Inc.Inventors: Jianhua Hu, Heng Kai Hsu, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
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Publication number: 20150311397Abstract: Transparent ohmic contacts to p-GaN and other high-work-function (?4.2 eV) semiconductors are fabricated from zinc stannate (e.g., ZnSnO3). ZnO and SnO2 may be sputtered from separate targets and annealed to form the zinc stannate. The Zn:Sn ratio may be tuned over the range between 1:2 and 2:1 to optimize bandgap, work function, conductivity, and transparency for the particular semiconductor and wavelength of interest. Conductivity may be improved by crystallizing the zinc stannate, by doping with up to 5 wt % Al or In, or both.Type: ApplicationFiled: April 23, 2014Publication date: October 29, 2015Applicant: INTERMOLECULAR, INC.Inventors: Jianhua Hu, Heng Kai Hsu, Tong Ju, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
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Patent number: 9112095Abstract: In some embodiments, Cu—In—Ga precursor films are deposited by co-sputtering from multiple targets. Specifically, the co-sputtering method is used to form layers that include In. The co-sputtering reduces the tendency for the In component to agglomerate and results in smoother, more uniform films. In some embodiments, the Ga concentration in one or more target(s) is between about 25 atomic % and about 66 atomic %. The deposition may be performed in a batch or in-line deposition system. If an in-line deposition system is used, the movement of the substrates through the system may be continuous or may follow a “stop and soak” method of substrate transport.Type: GrantFiled: December 14, 2012Date of Patent: August 18, 2015Assignee: Intermolecular, Inc.Inventors: Teresa B. Sapirman, Philip A. Kraus, Sang M. Lee, Haifan Liang, Jeroen Van Duren
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Patent number: 9012261Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate electrode deposition, gate electrode patterning, gate dielectric deposition, gate dielectric patterning, metal-based semiconductor material (e.g. IGZO) deposition, metal-based semiconductor material (e.g. IGZO) patterning, etch stop deposition, etch stop patterning, source/drain deposition, source/drain patterning, passivation deposition, or passivation patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.Type: GrantFiled: December 2, 2013Date of Patent: April 21, 2015Assignee: Intermolecular, Inc.Inventors: Jeroen Van Duren, Sang Lee, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
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Publication number: 20150091032Abstract: Diffusion of silver from LED reflector layers is blocked by 10-50 nm barrier layers of nickel-titanium (NiTi) alloys. Optionally, the alloys also include one or more of tungsten (W), niobium (Nb), aluminum (Al), vanadium (V), tantalum (Ta), or chromium (Cr). These barriers may omit the noble-metal (e.g., platinum or gold) cap used with silver barriers based on other materials.Type: ApplicationFiled: December 20, 2013Publication date: April 2, 2015Applicant: Intermolecular, Inc.Inventors: Jianhua Hu, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
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Publication number: 20150093500Abstract: The electrical and optical performance of silver LED reflective contacts in III-V devices such as GaN LEDs is limited by silver's tendency to agglomerate during annealing processes and to corrode on contact with silver-reactive materials elsewhere in the device (for example, gallium or aluminum). Agglomeration and reaction are prevented, and crystalline morphology of the silver layer may be optimized, by forming a diffusion-resistant transparent conductive layer between the silver and the source of silver-reacting metal, (2) doping the silver or the diffusion-resistant transparent conductive layer for improved adhesion to adjacent layers, or (3) doping the silver with titanium, which in some embodiments prevents agglomeration and promotes crystallization of the silver in the preferred <111> orientation.Type: ApplicationFiled: December 20, 2013Publication date: April 2, 2015Applicant: Intermolecular, Inc.Inventors: Teresa B. Sapirman, Jianhua Hu, Minh Huu Le
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Publication number: 20140273340Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate electrode deposition, gate electrode patterning, gate dielectric deposition, gate dielectric patterning, metal-based semiconductor material (e.g. IGZO) deposition, metal-based semiconductor material (e.g. IGZO) patterning, etch stop deposition, etch stop patterning, source/drain deposition, source/drain patterning, passivation deposition, or passivation patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.Type: ApplicationFiled: December 2, 2013Publication date: September 18, 2014Applicant: Intermolecular, Inc.Inventors: Jeroen Van Duren, Sang Lee, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
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Publication number: 20140170803Abstract: In some embodiments, Cu—In—Ga precursor films are deposited by co-sputtering from multiple targets. Specifically, the co-sputtering method is used to form layers that include In. The co-sputtering reduces the tendency for the In component to agglomerate and results in smoother, more uniform films. In some embodiments, the Ga concentration in one or more target(s) is between about 25 atomic % and about 66 atomic %. The deposition may be performed in a batch or in-line deposition system. If an in-line deposition system is used, the movement of the substrates through the system may be continuous or may follow a “stop and soak” method of substrate transport.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: INTERMOLECULAR, INC.Inventors: Teresa B. Sapirman, Philip A. Kraus, Sang M. Lee, Haifan Liang, Jeroen Van Duren