Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.

Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.

Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.

Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.

Abstract: Various implementations described herein are directed to a scan cell. The scan cell may include an input phase having multiple multiplexers and a latch arranged to receive a scan input signal, a first address signal, and a second address signal and provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a selection enable signal. The scan cell may include an output phase having multiple latches arranged to receive the scan input signal, the first address signal, or the second address signal from the input phase and provide the scan input signal, the first address signal, or the second address signal as a scan output signal based on a second clock signal and a third clock signal.

Abstract: Various implementations described herein are directed to a scan cell. The scan cell may include an input phase having multiple multiplexers and a latch arranged to receive a scan input signal, a first address signal, and a second address signal and provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a selection enable signal. The scan cell may include an output phase having multiple latches arranged to receive the scan input signal, the first address signal, or the second address signal from the input phase and provide the scan input signal, the first address signal, or the second address signal as a scan output signal based on a second clock signal and a third clock signal.

Abstract: An integrated circuit 2 is provided with a serial scan chain. Disposed between at least some serial scan cells 32, 34 forming a serial scan chain there is provided a partial scan cells 36. These partial scan cells are arranged such that during a scan mode in which serial data is being shifted into and out of the serial scan cells, a fixed value is captured and stored into the partial scan cell 36. This avoids the presence of unknown data values within the signal paths between the functional logic 38, 40 which is to be tested.

Abstract: An integrated circuit 2 is provided with a serial scan chain. Disposed between at least some serial scan cells 32, 34 forming a serial scan chain there is provided a partial scan cells 36. These partial scan cells are arranged such that during a scan mode in which serial data is being shifted into and out of the serial scan cells, a fixed value is captured and stored into the partial scan cell 36. This avoids the presence of unknown data values within the signal paths between the functional logic 38, 40 which is to be tested.

Abstract: An integrated circuit is formed of a plurality of circuit dies 22, 24 having through silicon vias (TSVs) passing there-through. The placement patterns of the through silicon vias differ between the circuit dies. An inter-die routing layer is provided either in a face of a substrate of one of the circuit dies or in an outer face of a layer of processing circuitry of one of the circuit dies. The inter-die routing layer bridges the gaps between the vias and the connection points of different circuit dies. The inter-die routing layer may be formed of metal tracks.

Abstract: An integrated circuit 2 provided with multiple functional units 6, 8, 10, 12, 14, and 16 for performing data processing operations as part of advancing execution of a data processing task by the integrated circuit 2. Activity detection circuitry 26 determines which of these functional circuits is inactive at the given time. If a functional is inactive, then scan control circuitry 28 may perform a scan test operation thereon using an associated serial scan chain 34, 36, 38, 40, 42, 44.

Abstract: An integrated circuit 2 provided with multiple functional units 6, 8, 10, 12, 14, and 16 for performing data processing operations as part of advancing execution of a data processing task by the integrated circuit 2. Activity detection circuitry 26 determines which of these functional circuits is inactive at the given time. If a functional is inactive, then scan control circuitry 28 may perform a scan test operation thereon using an associated serial scan chain 34, 36, 38, 40, 42, 44.

Abstract: A scan chain cell 24 is provided with a built-in delay testing capability. An inverter 32 generates an inverted form of the cell output which is available within the scan chain cell 24 for rapid use in forming a transition at the cell output Q. Clock gating circuitry 36, 38 is responsive to a hold signal to block the functional path 34, 26, 28 through the scan chain cell and hold the output signal when desired. The functional clock clk may be clocked twice at speed to trigger capture of the results of processing the output of the scan chain cell 24 for the non-inverted value followed by the (internally generated) inverted value, i.e. a signal transition. In this way delay testing of the functional circuitry 18 can be performed.

Abstract: A scan chain cell 24 is provided with a built-in delay testing capability. An inverter 32 generates an inverted form of the cell output which is available within the scan chain cell 24 for rapid use in forming a transition at the cell output Q. Clock gating circuitry 36, 38 is responsive to a hold signal to block the functional path 34, 26, 28 through the scan chain cell and hold the output signal when desired. The functional clock clk may be clocked twice at speed to trigger capture of the results of processing the output of the scan chain cell 24 for the non-inverted value followed by the (internally generated) inverted value, i.e. a signal transition. In this way delay testing of the functional circuitry 18 can be performed.

Abstract: A wrapper serial scan chain used during test of an integrated circuit is provided for a first functional block of circuitry and is segmented to provide a separately accessible wrapper serial scan chain segment that can be used to apply test to a second functional block of circuitry while bypassing the rest of the main wrapper serial scan chain.

Abstract: Testing of the test signal connections to a functional block of circuitry within an integrated circuit is made using wrapper serial scan chain cells of a wrapper serial scan chain. These wrapper cells can then be used to validate that the correct signals are reaching test signal inputs and the correct signals are reaching their destination from test signal outputs when that functional block of circuitry is incorporated within a larger design, e.g., a system-on-chip design.

Abstract: Within an integrated circuit 2 a functional block of circuitry 6 has an associated test wrapper circuit 10. The functional block of circuitry 6 includes functional latches 14 at least some of which may also serve as shared test latches 18 within the test wrapper circuitry 10. Separate reset signals reset_wrp, reset_int are generated for the test latches and shared test latches 18 as distinct from the functional latches 14. Thus, during testing, power consuming activity of the functional latches 14 can be suppressed if it is not desired to test the functional block of circuitry 6 itself. This is a particularly useful technique when a functional block of circuitry 6 is required to operate in an extest mode in which output signals from it are required to be driven so that other elements in the overall design may be tested and yet the internal action of the functional block of circuity 6 is not under test.

Abstract: In order to test the memory access signal connections between a data processing circuit, such as a processor core 2, and a memory 4, a subset of memory access signal connections 8 are provided with associated scan chain cells 10 so that they may be directly tested. The remainder memory access signal connections 12 which are common to all the expected configurations of the memory 4 are tested by being driven by the processor core 2 itself with data being passed through the memory and captured back within the processor core 2 for checking.

Abstract: Within an integrated circuit 2 a functional block of circuitry 6 has an associated test wrapper circuit 10. The functional block of circuitry 6 includes functional latches 14 at least some of which may also serve as shared test latches 18 within the test wrapper circuitry 10. Separate reset signals reset_wrp, reset_int are generated for the test latches and shared test latches 18 as distinct from the functional latches 14. Thus, during testing, power consuming activity of the functional latches 14 can be suppressed if it is not desired to test the functional block of circuitry 6 itself. This is a particularly useful technique when a functional block of circuitry 6 is required to operate in an extest mode in which output signals from it are required to be driven so that other elements in the overall design may be tested and yet the internal action of the functional block of circuity 6 is not under test.

Abstract: Testing of the test signal connections to a functional block of circuitry within an integrated circuit is made using wrapper serial scan chain cells of a wrapper serial scan chain such that it may be validated that the correct signals are reaching test signal inputs and the correct signals are reaching their destination from test signal outputs when that functional block of circuitry is incorporated within a larger design, such as a system-on-chip design.