Patents by Inventor Teresa Yim

Teresa Yim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7323413
    Abstract: An apparatus and a method for stripping silicon nitride are disclosed that facilitate automatic, real-time, and exact measurement of etch rate and an ending time of the etching process when silicon nitride is stripped with phosphoric acid solution. The method for stripping silicon nitride includes the steps of: a) measuring initial concentration of a specific ion in a phosphoric acid solution contained in a reactor, b) dipping a silicon nitride-formed substrate into the phosphoric acid solution in the reactor, c) measuring instantaneous concentration of the specific ion in stripping solution extracted from the reactor when silicon nitride stripping is processed in the reactor, and d) finishing the silicon nitride stripping process if variation rate of the measured instantaneous concentration is not exceeding a predetermined standard, or returning to the step c) if the variation rate is more than the predetermined standard.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: January 29, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Teresa Yim
  • Publication number: 20060057849
    Abstract: An apparatus and a method for stripping silicon nitride are disclosed that facilitate automatic, real-time, and exact measurement of etch rate and an ending time of the etching process when silicon nitride is stripped with phosphoric acid solution. The method for stripping silicon nitride includes the steps of: a) measuring initial concentration of a specific ion in a phosphoric acid solution contained in a reactor, b) dipping a silicon nitride-formed substrate into the phosphoric acid solution in the reactor, c) measuring instantaneous concentration of the specific ion in stripping solution extracted from the reactor when silicon nitride stripping is processed in the reactor, and d) finishing the silicon nitride stripping process if variation rate of the measured instantaneous concentration is not exceeding a predetermined standard, or returning to the step c) if the variation rate is more than the predetermined standard.
    Type: Application
    Filed: September 14, 2005
    Publication date: March 16, 2006
    Inventor: Teresa Yim
  • Publication number: 20060003101
    Abstract: A method of pre-cleaning a wafer for gate oxide formation is described. In the method, a wafer is loaded into a cleaning bath, and a cleaning agent such as diluted HF is supplied into the bath so as to remove contaminants from the back surface of the wafer. Then the cleaning agent is drained from the bath, and the wafer is rinsed with DI water. During this DI rinsing step, contaminants removed from the wafer may remain as impurities and bind to or combine with silicon on the front surface of the wafer. To remove such impurities from the wafer, a second cleaning agent is supplied again into the bath. After removal, the second cleaning agent is drained from the bath, and the wafer is rinsed again with DI water. Finally, and optionally, the wafer may be treated with HCl and ozone.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 5, 2006
    Inventors: Teresa Yim, Byoung Seo, Yong Hoh
  • Patent number: 6974756
    Abstract: A method of forming a shallow trench isolation is disclosed. An example method of forming a shallow trench isolation performs a planarization process for a substrate on which a hard mask and an insulation layer are formed, selectively etching the insulation layer on the edge of the substrate by using wet etch equipment, and performs a main etching process in the center region of the substrate.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: December 13, 2005
    Assignee: DongbuAnam Semiconductor, Inc.
    Inventor: Teresa Yim
  • Publication number: 20050136614
    Abstract: A method of forming a shallow trench isolation is disclosed. An example method of forming a shallow trench isolation performs a planarization process for a substrate on which a hard mask and an insulation layer are formed, selectively etching the insulation layer on the edge of the substrate by using wet etch equipment, and performs a main etching process in the center region of the substrate.
    Type: Application
    Filed: December 23, 2004
    Publication date: June 23, 2005
    Inventor: Teresa Yim