Patents by Inventor Terh Kuen Yii

Terh Kuen Yii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8736042
    Abstract: A semiconductor package configured to attain a thin profile and low moisture sensitivity. Packages of this invention can include a semiconductor die mounted on a die attachment site of a leadframe and further connected with a plurality of elongate I/O leads arranged about the die attach pad and extending in said first direction. The leadframe having an “up-set” bonding pad arranged with a bonding support for supporting a plurality of wire bonds and a large mold flow aperture in the up-set bonding pad. The package encapsulated in a mold material that surrounds the bonding support and flows through the large mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: May 27, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Felix C. Li, Yee Kim Lee, Peng Soon Lim, Terh Kuen Yii, Lee Han Meng@Eugene Lee
  • Publication number: 20120080781
    Abstract: A semiconductor package configured to attain a thin profile and low moisture sensitivity. Packages of this invention can include a semiconductor die mounted on a die attachment site of a leadframe and further connected with a plurality of elongate I/O leads arranged about the die attach pad and extending in said first direction. The leadframe having an “up-set” bonding pad arranged with a bonding support for supporting a plurality of wire bonds and a large mold flow aperture in the up-set bonding pad. The package encapsulated in a mold material that surrounds the bonding support and flows through the large mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity.
    Type: Application
    Filed: December 13, 2011
    Publication date: April 5, 2012
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Felix C. LI, Yee Kim LEE, Peng Soon LIM, Terh Kuen YII, Lee Han Meng@Eugene LEE
  • Patent number: 8097934
    Abstract: A lead frame and package construction configured to attain a thin profile and low moisture sensitivity. Lead frames of this invention may include a die attach pad having a die attachment site and an elongate ground lead that extends from the die attach pad. The lead frame includes a plurality of elongate I/O leads arranged about the die attach pad and extending away from the die attach pad in at least two directions. An inventive lead frame features “up-set” bonding pads electrically connected with the die attach pad and arranged with a bonding surface for supporting a plurality of wire bonds. The bonding surfaces also constructed to define at least one mold flow aperture for each up-set bonding pad. A package incorporating the lead frame is further disclosed such that the package includes an encapsulant that surrounds the bonding support and flows through the mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: January 17, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Felix C. Li, Yee Kim Lee, Peng Soon Lim, Terh Kuen Yii, Lee Han Meng@Eugene Lee
  • Patent number: 7838980
    Abstract: A lead frame and package construction configured to attain a thin profile and low moisture sensitivity. Lead frames of this invention may include a die attach pad having a die attachment site and an elongate ground lead that extends from the die attach pad. The lead frame includes a plurality of elongate I/O leads arranged about the die attach pad and extending in said first direction. An inventive lead frame features an “up-set” bonding pad electrically connected with the die attach pad and arranged with a bonding support for supporting a plurality of wire bonds. The lead frame also having a large mold flow aperture in the up-set bonding pad. A package incorporating the lead frame is further disclosed such that the package includes an encapsulant that surrounds the bonding support and flows through the large mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 23, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Yee Kim Lee, Peng Soon Lim, Terh Kuen Yii, Lee Han Meng@Eugene Lee
  • Patent number: 7763958
    Abstract: An improved leadframe panel suitable for use in packaging IC dice for use in power applications is described. The described leadframe panel enables more efficient means of encapsulation and singulation as compared with a conventional power leadframe panel. Additionally, a thin IC power package is described that enables increased package heat dissipation, the use of a larger die attach pad as well as the use of a larger die as compared with conventional power devices.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: July 27, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Peng Soon Lim, Terh Kuen Yii, Sek Hoi Chong
  • Patent number: 7714418
    Abstract: An improved leadframe panel suitable for use in packaging IC dice is described. The described leadframe panel is configured such that the amount of leadframe material that is removed during singulation of the leadframe panel is reduced.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: May 11, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Peng Soon Lim, Terh Kuen Yii, Mohd Sabri Bin Mohamad Zin, Ken Pham
  • Patent number: 7582954
    Abstract: Apparatuses and methods directed to a semiconductor chip package having an optical component are disclosed. Packages include a die having a light sensing region and a stress buffer on a first surface, a first opaque encapsulant having an opening therethrough disposed atop the first surface, and a second transparent or translucent encapsulant formed within the first encapsulant opening and directly atop and contacting the light sensing region. A leadless leadframe or other conductive component can be coupled to a second surface of the die. The die may also have light sensitive regions that are shielded by the first encapsulant and/or stress buffer. The stress buffer can be a layer formed at the wafer stage or a dam formed at the panel stage. A customized mold is used while dispensing the first encapsulant such that the opening therethrough is properly formed.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: September 1, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Peng Soon Lim, Terh Kuen Yii, You Chye How, Sek Hoi Chong, Shee Min Yeong
  • Publication number: 20090212382
    Abstract: Apparatuses and methods directed to a semiconductor chip package having an optical component are disclosed. Packages include a die having a light sensing region and a stress buffer on a first surface, a first opaque encapsulant having an opening therethrough disposed atop the first surface, and a second transparent or translucent encapsulant formed within the first encapsulant opening and directly atop and contacting the light sensing region. A leadless leadframe or other conductive component can be coupled to a second surface of the die. The die may also have light sensitive regions that are shielded by the first encapsulant and/or stress buffer. The stress buffer can be a layer formed at the wafer stage or a dam formed at the panel stage. A customized mold is used while dispensing the first encapsulant such that the opening therethrough is properly formed.
    Type: Application
    Filed: February 25, 2008
    Publication date: August 27, 2009
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Peng Soon LIM, Terh Kuen YII, You Chye HOW, Sek Hoi CHONG, Shee Min YEONG
  • Publication number: 20090026590
    Abstract: An improved leadframe panel suitable for use in packaging IC dice is described. The described leadframe panel is configured such that the amount of leadframe material that is removed during singulation of the leadframe panel is reduced.
    Type: Application
    Filed: July 23, 2007
    Publication date: January 29, 2009
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Peng Soon LIM, Terh Kuen YII, Mohd Sabri ZIN, Ken PHAM