Patents by Inventor Tero Karras

Tero Karras has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200302676
    Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.
    Type: Application
    Filed: June 4, 2020
    Publication date: September 24, 2020
    Inventors: Samuli LAINE, Timo AILA, Tero KARRAS, Gregory MUTHLER, William P. NEWHALL, JR., Ronald C. BABICH, JR., Craig KOLB, Ignacio LLAMAS, John BURGESS
  • Patent number: 10740952
    Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to provide a deterministic result of intersected triangles regardless of the order that the memory subsystem returns triangle range blocks for processing, while opportunistically eliminating alpha intersections that lie further along the length of the ray than closer opaque intersections.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: August 11, 2020
    Assignee: NVIDIA Corporation
    Inventors: Samuli Laine, Tero Karras, Greg Muthler, William Parsons Newhall, Jr., Ronald Charles Babich, Ignacio Llamas, John Burgess
  • Publication number: 20200242736
    Abstract: A few-shot, unsupervised image-to-image translation (“FUNIT”) algorithm is disclosed that accepts as input images of previously-unseen target classes. These target classes are specified at inference time by only a few images, such as a single image or a pair of images, of an object of the target type. A FUNIT network can be trained using a data set containing images of many different object classes, in order to translate images from one class to another class by leveraging few input images of the target class. By learning to extract appearance patterns from the few input images for the translation task, the network learns a generalizable appearance pattern extractor that can be applied to images of unseen classes at translation time for a few-shot image-to-image translation task.
    Type: Application
    Filed: January 29, 2019
    Publication date: July 30, 2020
    Inventors: Ming-Yu Liu, Xun Huang, Tero Karras, Timo Aila, Jaakko Lehtinen
  • Publication number: 20200160588
    Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to omit reporting of one or more primitives the ray is determined to intersect. The omitted primitives include primitives which are provably capable of being omitted without a functional impact on visualizing the virtual scene.
    Type: Application
    Filed: January 22, 2020
    Publication date: May 21, 2020
    Inventors: Greg MUTHLER, Tero KARRAS, Samuli LAINE, William Parsons NEWHALL, JR., Ronald Charles BABICH, JR., John BURGESS, Ignacio LLAMAS
  • Patent number: 10580196
    Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to omit reporting of one or more primitives the ray is determined to intersect. The omitted primitives include primitives which are provably capable of being omitted without a functional impact on visualizing the virtual scene.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: March 3, 2020
    Assignee: NVIDIA Corporation
    Inventors: Greg Muthler, Tero Karras, Samuli Laine, William Parsons Newhall, Jr., Ronald Charles Babich, Jr., John Burgess, Ignacio Llamas
  • Publication number: 20200051315
    Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Samuli Laine, Timo AILA, Tero KARRAS, Gregory MUTHLER, William Parsons NEWHALL, JR., Ronald Charles BABICH, JR., Craig KOLB, Ignacio LLAMAS
  • Publication number: 20200050550
    Abstract: In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Greg MUTHLER, Timo AILA, Tero KARRAS, Samuli LAINE, William Parsons NEWHALL, Ronald Charles BABICH, John BURGESS, Ignacio LLAMAS
  • Publication number: 20200051314
    Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Samuli Laine, Tero Karras, Timo Aila, Robert Ohannessian, William Parsons Newhall, JR., Greg Muthler, Ian Kwong, Peter Nelson, John Burgess
  • Publication number: 20200051316
    Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to provide a deterministic result of intersected triangles regardless of the order that the memory subsystem returns triangle range blocks for processing, while opportunistically eliminating alpha intersections that lie further along the length of the ray than closer opaque intersections.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Samuli LAINE, Tero KARRAS, Greg MUTHLER, William Parsons NEWHALL, JR., Ronald Charles BABICH, Ignacio LLAMAS, John BURGESS
  • Publication number: 20200051312
    Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to omit reporting of one or more primitives the ray is determined to intersect. The omitted primitives include primitives which are provably capable of being omitted without a functional impact on visualizing the virtual scene.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Greg Muthler, Tero Karras, Samuli Laine, William Parsons Newhall, JR., Ronald Charles Babich, JR., John Burgess, Ignacio Llamas
  • Publication number: 20200050451
    Abstract: Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Ronald Babich, John BURGESS, Jack CHOQUETTE, Tero KARRAS, Samuli LAINE, Ignacio LLAMAS, Gregory MUTHLER, William Parsons NEWHALL, JR.
  • Patent number: 9965821
    Abstract: A system and method for constructing binary radix trees in parallel, which are used for as a building block for constructing secondary trees. A non-transitory computer-readable storage medium having computer-executable instructions for causing a computer system to perform a method is disclosed. The method includes determining a plurality of primitives comprising a total number of primitive nodes that are indexed, wherein the plurality of primitives correspond to leaf nodes of a hierarchical tree. The method includes sorting the plurality of primitives. The method includes building the hierarchical tree in a manner requiring at most a linear amount of temporary storage with respect to the total number of primitive nodes. The method includes building an internal node of the hierarchical tree in parallel with one or more of its ancestor nodes.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: May 8, 2018
    Assignee: NVIDIA CORPORATION
    Inventor: Tero Karras
  • Patent number: 9721320
    Abstract: A non-transitory computer-readable storage medium having computer-executable instructions for causing a computer system to perform a method for constructing bounding volume hierarchies from binary trees is disclosed. The method includes providing a binary tree including a plurality of leaf nodes and a plurality of internal nodes. Each of the plurality of internal nodes is uniquely associated with two child nodes, wherein each child node comprises either an internal node or leaf node. The method also includes determining a plurality of bounding volumes for nodes in the binary tree by traversing the binary tree from the plurality of leaf nodes upwards toward a root node, wherein each parent node is processed once by a later arriving corresponding child node.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: August 1, 2017
    Assignee: NVIDIA CORPORATION
    Inventor: Tero Karras
  • Patent number: 9437039
    Abstract: A method of generating an image. The method includes simulating a presence of at least one light source within a virtualized three dimensional space. Within the virtualized three dimensional space, a light sensing plane is defined. The light sensing plane includes a matrix of a number of pixels to be displayed on a display screen. The method further includes using a light transport procedure, computing a gradient value for each pixel of the matrix to produce a number of gradient values. The gradient computation involves selecting a plurality of light path pairs that contribute to a pixel wherein the selection is biased towards selection of more light paths that pass through pixels having larger gradient values. The plurality of gradient values are converted to a plurality of light intensity values which represent the image.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 6, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Jaakko Lehtinen, Timo Aila, Samuli Laine, Tero Karras, David Luebke
  • Patent number: 9396512
    Abstract: A non-transitory computer-readable storage medium having computer-executable instructions for causing a computer system to perform a method for constructing k-d trees, octrees, and quadtrees from radix trees is disclosed. The method includes assigning a Morton code for each of a plurality of primitives corresponding to leaf nodes of a binary radix tree, and sorting the plurality of Morton codes. The method includes building a radix tree requiring at most a linear amount of temporary storage with respect to the leaf nodes, wherein an internal node is built in parallel with one or more of its ancestor nodes. The method includes, partitioning the plurality of Morton codes for each node of the radix tree into categories based on a corresponding highest differing bit to build a k-d tree. A number of octree or quadtree nodes is determined for each node of the k-d tree. A total number of nodes in the octree or quadtree is determined, allocated and output.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 19, 2016
    Assignee: NVIDIA CORPORATION
    Inventor: Tero Karras
  • Patent number: 9269183
    Abstract: A method for reducing the number of samples tested for rendering a screen space region of an image includes constructing a bilinear approximation per primitive for a screen space region which is to be rendered, wherein the screen space region includes a plurality of sample points. The bilinear approximation is used to estimate coverage of a predefined primitive against one or more sample points within the screen space region. At least one sample point in the screen space region which is not covered by the predefined primitive is excluded from testing in the rendering of the screen space region.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: February 23, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Samuli Laine, Tero Karras
  • Patent number: 9153068
    Abstract: A method for reducing the number of samples tested for rendering a screen space region of an image includes constructing a trajectory of a primitive extending in an image which is to be rendered. A bounding volume is constructed for a screen space region of the image, the bounding volume characterized as having a bound in a non-screen space dimension which is defined as a function of the primitive's trajectory. The bounding volume is further characterized as overlapping a portion of the screen space region which is to be rendered. One or more sample points which are located within the screen space region, and which are not overlapped by the bounding volume are excluded from testing.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: October 6, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Samuli Laine, Tero Karras, Jaakko Lehtinen, Timo Aila
  • Patent number: 9142043
    Abstract: A method for reducing the number of samples tested for rendering a screen space region of an image includes constructing a trajectory of a primitive extending within an image which is to be rendered. A bounding volume is constructed for a screen space region of the image, the bounding volume characterized as having a bound in a non-screen space dimension which is defined as a function of the primitive's trajectory. The bounding volume is further characterized as overlapping a portion of the screen space region which is to be rendered. One or more sample points which are located within the screen space region, and which are not overlapped by the bounding volume are excluded from testing.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: September 22, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Timo Aila, Samuli Laine, Tero Karras, Jaakko Lehtinen, Peter Shirley
  • Patent number: 8698836
    Abstract: A system, method, and computer program product are provided for optimizing stratified sampling associated with stochastic transparency. In use, surface data associated with one or more surfaces to be rendered is received. Additionally, the one or more surfaces are rendered, utilizing stochastic transparency, where stratified sampling associated with the stochastic transparency is optimized.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: April 15, 2014
    Assignee: NVIDIA Corporation
    Inventors: Samuli Laine, Tero Karras
  • Publication number: 20140071129
    Abstract: A method of generating an image. The method includes simulating a presence of at least one light source within a virtualized three dimensional space. Within the virtualized three dimensional space, a light sensing plane is defined. The light sensing plane includes a matrix of a number of pixels to be displayed on a display screen. The method further includes using a light transport procedure, computing a gradient value for each pixel of the matrix to produce a number of gradient values. The gradient computation involves selecting a plurality of light path pairs that contribute to a pixel wherein the selection is biased towards selection of more light paths that pass through pixels having larger gradient values. The plurality of gradient values are converted to a plurality of light intensity values which represent the image.
    Type: Application
    Filed: December 28, 2012
    Publication date: March 13, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Jaakko Lehtinen, Timo Aila, Samuli Laine, Tero Karras, David Luebke