Abstract: An apparatus, computer readable medium, and method are disclosed for decompressing compressed geometric data stored in a lossless compression format. The compressed geometric data resides within a compression block sized according to a system cache line. An indirection technique maps a global identifier value in a linear identifier space to corresponding variable rate compressed data. The apparatus may include decompression circuitry within a graphics processing unit configured to perform ray-tracing.

Abstract: A system, method, and computer program product for implementing a tree traversal operation for a tree data structure divided into compression blocks is disclosed. The method includes the steps of receiving at least a portion of a tree data structure that represents a tree having a plurality of nodes, pushing a root node of the tree data structure onto a traversal stack data structure associated with an outer loop of a tree traversal operation algorithm, and, for each iteration of an outer loop of a tree traversal operation algorithm, popping a top element from the traversal stack data structure and processing, via an inner loop of the tree traversal operation algorithm, the compression block data structure that corresponds with the top element. The tree data structure may be encoded as a plurality of compression block data structures that each include data associated with a subset of nodes of the tree.

Abstract: One embodiment sets forth a technique for scheduling the execution of ordered critical code sections by multiple threads. A multithreaded processor includes an instruction scheduling unit that is configured to schedule threads to process ordered critical code sections. A ordered critical code section is preceded by a barrier instruction and when all of the threads have reached the barrier instruction, the instruction scheduling unit controls the thread execution order by selecting each thread for execution based on logical identifiers associated with the threads. The logical identifiers are mapped to physical identifiers that are referenced by the multithreaded processor during execution of the threads. The logical identifiers are used by the instruction scheduling unit to control the order in which the threads execute the ordered critical code section.

Abstract: A system, method, and computer program product are provided for subdividing a quadratic Bezier curve. The method includes the steps of receiving a quadratic Bezier curve defined by a plurality of control points including at least a first endpoint and a second endpoint. The quadratic Bezier curve is uniformly subdivided based on an angle between a first tangent at the first endpoint and a second tangent at the second endpoint to produce a piecewise representation of the quadratic Bezier curve including two or more Bezier curve segments.

Abstract: A system, method, and computer program product are provided for modifying a hierarchical tree data structure. An initial hierarchical tree data structure is received, and treelets of node neighborhoods are formed. A processor restructures the treelets using agglomerative clustering to produce an optimized hierarchical tree data structure that includes at least one restructured treelet, where each restructured treelet includes at least one internal node.

Abstract: A system, method, and computer program product are provided for modifying a hierarchical tree data structure. An initial hierarchical tree data structure is received and treelets of node neighborhoods in the initial hierarchical tree data structure are formed. Each treelet includes n leaf nodes and n?1 internal nodes. The treelets are restructured, by a processor, to produce an optimized hierarchical tree data structure.

Abstract: A system, method, and computer program product are provided for splitting primitives. A plurality of primitives is received for a scene and a pre-determined plane that intersects the scene is identified. Bounding volumes of the plurality of primitives that are intersected by the pre-determined plane are split, where a bounding volume that encloses each intersected primitive of the plurality of primitives is split into a first bounding volume and a second bounding volume at an intersection of the bounding volume and the pre-determined plane.

Abstract: This disclosure is directed to systems and methods for sorting data in which pre-sorting operations are performed on keys prior to those keys being reordered within memory. One example method includes generating, for each of a plurality of keys, an associated modified key. This operation is an example pre-sorting operation that occurs prior to any reordering of the keys. Once the modified keys are generated, the modified keys and/or associated information are processed in order to change the ordering of the keys in memory.

Abstract: A system, method, and computer program product are provided for utilizing a wavefront path tracer. In use, a set of light transport paths associated with a scene is identified. Additionally, parallel path tracing is performed, utilizing a wavefront path tracer.

Abstract: A system, method, and computer program product are provided for conservative rasterization of primitives using an error term. In use, an edge equation is determined for each edge of a primitive, the edge equation having coefficients defining the edge of the primitive. Each edge of the primitive is shifted to enlarge the primitive by modifying coefficients of the edge equation defining the edge by an error term that is a predetermined amount. Pixels that intersect the primitive are then determined using the enlarged primitive.

Abstract: A method and a system are provided for hardware scheduling of indexed barrier instructions. Execution of a plurality of threads to process instructions of a program that includes a barrier instruction is initiated and when each thread reaches the barrier instruction, the thread pauses execution of the instructions. A first sub-group of threads in the plurality of threads is associated with a first sub-barrier index and a second sub-group of threads in the plurality of threads is associated with a second sub-barrier index. When the barrier instruction can be scheduled for execution, threads in the first sub-group are executed serially and threads in the second sub-group are executed serially and at least one thread in the first sub-group is executed in parallel with at least one thread in the second sub-group.

Abstract: A method and a system are provided for hardware scheduling of barrier instructions. Execution of a plurality of threads to process instructions of a program that includes a barrier instruction is initiated, and when each thread reaches the barrier instruction during execution of program, it is determined whether the thread participates in the barrier instruction. The threads that participate in the barrier instruction are then serially executed to process one or more instructions of the program that follow the barrier instruction. A method and system are also provided for impatient scheduling of barrier instructions. When a portion of the threads that is greater than a minimum number of threads and less than all of the threads in the plurality of threads reaches the barrier instruction each of the threads in the portion is serially executed to process one or more instructions of the program that follow the barrier instruction.

Abstract: One embodiment sets forth a technique for scheduling the execution of ordered critical code sections by multiple threads. A multithreaded processor includes an instruction scheduling unit that is configured to schedule threads to process ordered critical code sections. A ordered critical code section is preceded by a barrier instruction and when all of the threads have reached the barrier instruction, the instruction scheduling unit controls the thread execution order by selecting each thread for execution based on logical identifiers associated with the threads. The logical identifiers are mapped to physical identifiers that are referenced by the multithreaded processor during execution of the threads. The logical identifiers are used by the instruction scheduling unit to control the order in which the threads execute the ordered critical code section.