Patents by Inventor Terrance John Zittritsch
Terrance John Zittritsch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6130854Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: October 10, 2000Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Terrance John Zittritsch
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Patent number: 6118707Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 10, 1998Date of Patent: September 12, 2000Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Terrance John Zittritsch
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Patent number: 6075745Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: June 13, 2000Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 6038192Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 10, 1998Date of Patent: March 14, 2000Assignee: International Business Machines CorporationInventors: Kim P. N. Clinton, Joseph Andrew Iadanza, Frank Ray Keyser, III, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 6023421Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: February 8, 2000Assignee: International Business Machines CorporationInventors: Kim P. N. Clinton, Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Ralph David Kilmoyer, Michael Joseph Laramie, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 5949719Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: September 7, 1999Assignee: International Business Machines CorporationInventors: Kim P. N. Clinton, Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Ralph David Kilmoyer, Michael Joseph Laramie, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 5914906Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: December 20, 1995Date of Patent: June 22, 1999Assignee: International Business Machines CorporationInventors: Joseph Andrew Iadanza, Ralph David Kilmoyer, Michael Joseph Laramie, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 5910733Abstract: A method and system for defining, placing and routing kernels for a family of integrated circuits is provided. The integrated circuits are defined using repeatable row and column circuit types. Kernels are defined by the intersections of the row and column circuit types in the array. The kernels are placed and routed automatically for each member of the family of integrated circuit arrays, each member being generally characterized by a different size, i.e., a different number of repeatable row or column circuit types.Type: GrantFiled: November 12, 1997Date of Patent: June 8, 1999Assignee: International Business Machines CorporationInventors: Allan Robert Bertolet, Kim P.N. Clinton, Scott Whitney Gould, Frank Ray Keyser III, Timothy Shawn Reny, Terrance John Zittritsch
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Patent number: 5781032Abstract: A programmable logic cell has four cell input nodes and a plurality of combinational logic circuits. Four inverter circuits are provided for programmably inverting respective input logic signals, each inverter circuit having an inverter input node connected to a respective cell input node for accepting its respective input logic signal therefrom. Each inverter is programmable into a first state wherein a logic signal representing the complement of the input logic signal is provided to the inverter output node, and a second state wherein a logic signal representing the non-complement of the input logic signal is provided to the inverter output node. The inverter circuits buffer their input logic signals in both their first and second states.Type: GrantFiled: September 9, 1996Date of Patent: July 14, 1998Assignee: International Business Machines CorporationInventors: Allan Robert Bertolet, Kim P.N. Clinton, Christine Marie Fuller, Scott Whitney Gould, Steven Paul Hartman, Joseph Andrew Iadanza, Frank Ray Keyser, Eric Ernest Millham, Timothy Shawn Reny, Brian A. Worth, Gulson Yasar, Terrance John Zittritsch
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Patent number: 5748009Abstract: A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g.Type: GrantFiled: September 9, 1996Date of Patent: May 5, 1998Assignee: International Business Machines CorporationInventors: Allan Robert Bertolet, Kim P. N. Clinton, Christine Marie Fuller, Scott Whitney Gould, Steven Paul Hartman, Joseph Andrew Iadanza, Frank Ray Keyser, Eric Ernest Millham, Timothy Shawn Reny, Brian A. Worth, Gulson Yasar, Terrance John Zittritsch
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Patent number: 5734582Abstract: A method and system for defining, placing and routing kernels for a family of integrated circuits is provided. The integrated circuits are defined using repeatable row and column circuit types. Kernels are defined by the intersections of the row and column circuit types in the array. The kernels are placed and routed automatically for each member of the family of integrated circuit arrays, each member being generally characterized by a different size, i.e., a different number of repeatable row or column circuit types.Type: GrantFiled: December 12, 1995Date of Patent: March 31, 1998Assignee: International Business Machines CorporationInventors: Allan Robert Bertolet, Kim P. N. Clinton, Scott Whitney Gould, Frank Ray Keyser, III, Timothy Shawn Reny, Terrance John Zittritsch
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Patent number: 5717346Abstract: A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.Type: GrantFiled: September 6, 1996Date of Patent: February 10, 1998Assignees: International Business Machines Corporation, Atmel CorporationInventors: Scott Whitney Gould, Frederick Curtis Furtek, Frank Ray Keyser, III, Brian A. Worth, Terrance John Zittritsch
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Patent number: 5703498Abstract: A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.Type: GrantFiled: September 6, 1996Date of Patent: December 30, 1997Assignees: International Business Machines Corporation, Atmel CorporationInventors: Scott Whitney Gould, Frederick Curtis Furtek, Frank Ray Keyser, III, Brian A. Worth, Terrance John Zittritsch
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Patent number: 5671432Abstract: A programmable array having programmable logic cells, a programmable interconnect network and a programmable I/O system. Two I/O interfaces are provided for respective logic cells about the perimeter of the array. The I/O interfaces comprise input, output and enable paths. Each of these paths has an associated multiplexer. An I/O routing network is positioned about the perimeter of the array. Conductors connecting the I/O interface multiplexers to the programmable interconnect network also intersect, and can be programmably connected to, buses of the I/O routing network.Type: GrantFiled: June 2, 1995Date of Patent: September 23, 1997Assignees: International Business Machines Corporation, Cadence Design Systems, Inc.Inventors: Allan Robert Bertolet, Kenneth Ferguson, Scott Whitney Gould, Eric Ernest Millham, Ronald Raymond Palmer, Brian Worth, Terrance John Zittritsch
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Patent number: 5652529Abstract: A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering, and output driver sizing as a function of signal propagation distance.Type: GrantFiled: June 2, 1995Date of Patent: July 29, 1997Assignees: International Business Machines Corporation, Atmel CorporationInventors: Scott Whitney Gould, Frederick Curtis Furtek, Frank Ray Keyser, III, Brian A. Worth, Terrance John Zittritsch
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Patent number: 5646546Abstract: A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g.Type: GrantFiled: June 2, 1995Date of Patent: July 8, 1997Assignee: International Business Machines CorporationInventors: Allan Robert Bertolet, Kim P. N. Clinton, Christine Marie Fuller, Scott Whitney Gould, Steven Paul Hartman, Joseph Andrew Iadanza, Frank Ray Keyser, Eric Ernest Millham, Timothy Shawn Reny, Brian A. Worth, Gulson Yasar, Terrance John Zittritsch