Abstract: A test and measurement instrument including a plurality of digitizers, each digitizer configured to digitize an input signal to generate a digitized signal; a signal processor configured to combine at least two of the digitized signals from the digitizers into a combined signal; and a circuit configured to receive the combined signal.

Abstract: A waveform display apparatus and method displays one or more waveforms of a signal under test at high throughput while acquiring digital data of the signal under test in a large acquisition memory. A user sets a time interval of user's interest when viewing a signal under test and sets trigger criteria through a user interface. An ADC converts the signal under test into digital data that is stored in a large acquisition memory. A trigger unit detects and produces trigger events, based on a trigger, as trigger event information during one acquisition process. A trigger event eliminator may discard some of the trigger events based on pre-trigger and post-conditions set through the interface by a user. The trigger events are recorded in a trigger list as the trigger event information. A control unit locates the digital data in the acquisition memory corresponding to the trigger events in the trigger list and displays a waveform associated with the trigger event for the time interval on a display device.

Abstract: A digital storage oscilloscope employs an improved edge triggering circuit that discards some of trigger events when it determines that there are many more trigger events than the oscilloscope can use. The determination is made in response to detection of a characteristic of the signal that indicates a repetitive nature of a complex signal. Certain trigger events are selected to be acted upon, and others are discarded, in response to the determination. The circuitry dynamically reacts to changes in the input signal in response to detection of different criteria for a characteristic of repetition as the input signal changes.

Abstract: A fast rasterizer uses a fast memory that has a bit-set port for receiving data and a totally independent readout and clear port for outputting a waveform image. The fast memory is organized into rows and columns corresponding to the rows and columns of a raster display device, with each memory location or cell holding a single bit. The fast memory is divided into parallel sections so that one column of each section may be written into each clock cycle, resulting in the possibility of writing a plurality of columns into the fast memory each clock cycle. Each memory cell is set when a row and column write signal for the cell are asserted, and is read out and cleared when a row and column read signal for the cell are asserted. Row logic using thermometer codes is used to set the row lines for the selected column in each section.

Abstract: A waveform display apparatus and method displays one or more waveforms of a signal under test at high throughput while acquiring digital data of the signal under test in a large acquisition memory. A user sets a time interval of user's interest when viewing a signal under test and sets trigger criteria through a user interface. An ADC converts the signal under test into digital data that is stored in a large acquisition memory. A trigger unit detects and produces trigger events, based on a trigger, as trigger event information during one acquisition process. A trigger event eliminator may discard some of the trigger events based on pre-trigger and post-conditions set through the interface by a user. The trigger events are recorded in a trigger list as the trigger event information. A control unit locates the digital data in the acquisition memory corresponding to the trigger events in the trigger list and displays a waveform associated with the trigger event for the time interval on a display device.

Abstract: A test and measurement instrument including a plurality of digitizers, each digitizer configured to digitize an input signal to generate a digitized signal; a signal processor configured to combine at least two of the digitized signals from the digitizers into a combined signal; and a circuit configured to receive the combined signal.

Abstract: A “no dead time” data acquisition system for a measurement instrument receives a digitized signal representing an electrical signal being monitored and generates from the digitized signal a trigger signal using a fast digital trigger circuit, the trigger signal including all trigger events within the digitized signal. The digitized signal is compressed as desired and delayed by a first-in, first-out (FIFO) buffer for a period of time to assure a predetermined amount of data prior to a first trigger event in the trigger signal. The delayed digitized signal is delivered to a fast rasterizer or drawing engine upon the occurrence of the first trigger event to generate a waveform image. The waveform image is then provided to a display buffer for combination with prior waveforms and/or other graphic inputs from other drawing engines. The contents of the display buffer are provided to a display at a display update rate to show a composite of all waveform images representing the electrical signal.

Abstract: A noise rejection filter for a trigger circuit uses an algorithm that updates the filter output monotonically so long as the signal slope remains unchanged, maintains the filter output at a constant level when the signal slope changes but the difference between the sample value and the filter output is less than or equal to a hysteresis value, and changes the signal slope while updating the filter output when the difference is greater than the hysteresis value. This maintains the peaks of the input signal at the filter output. The noise rejection filter may be used in a trigger circuit prior to a comparator so that the trigger signal from the comparator accurately reflects the signal pulse width at a desired trigger level and trigger events are detected when the desired trigger level is near the peaks of the input signal.

Abstract: A data management method for a long record length memory that is used for data acquisition writes data samples into an initial circular buffer within the memory having a size equal to a pre-trigger time. When a first trigger event occurs, the data samples are then written into a linear region after the circular buffer within the memory. The data sample acquisition in the linear region continues until a post-trigger and new pre-trigger time have elapsed after a last trigger event, at which point the acquisition terminates and the new pre-trigger time becomes a new circular buffer for a next trigger event. In this way all trigger events are captured with associated pre-trigger and post-trigger data.

Abstract: A noise rejection filter for a trigger circuit uses an algorithm that updates the filter output monotonically so long as the signal slope remains unchanged, maintains the filter output at a constant level when the signal slope changes but the difference between the sample value and the filter output is less than or equal to a hysteresis value, and changes the signal slope while updating the filter output when the difference is greater than the hysteresis value. This maintains the peaks of the input signal at the filter output. The noise rejection filter may be used in a trigger circuit prior to a comparator so that the trigger signal from the comparator accurately reflects the signal pulse width at a desired trigger level and trigger events are detected when the desired trigger level is near the peaks of the input signal.

Abstract: An improved digital trigger circuit has a plurality of data samples extracted from an input electrical signal for each sample clock cycle. The plurality of data samples are compared in parallel with a high threshold level and a low threshold level which provides hysteresis for noise rejection. Also the plurality of data samples are used to determine sub-sample trigger positioning. The comparison outputs are input to a digital trigger logic circuit for identifying a selected trigger event and generating a trigger for the acquisition of data from the input electrical signal for analysis and display. The digital trigger logic provides edge event triggering, pulse width triggering and transition time triggering, among others.