Abstract: Power conservation in a phase locked loop (PLL) places the PLL into a low-power mode and periodically reactivates the PLL to prevent leakage current from causing a voltage controlled oscillator (VCO) within the PLL to drift. The PLL also includes an adjustable delay circuit positioned between an output of the VCO and an input of a phase detector, where the delay circuit is used to adjust phase slew of a feedback signal to help the PLL settle into a desired frequency. By controlling the drift of the VCO and keeping the phase slew of the feedback signal to a minimum, the PLL may be activated and settle to a desired frequency within a relatively short amount of time. By keeping this time so short, the PLL may be placed into and pulled out of a low-power mode and still meet rigid timing requirements of various transmission protocols.

Abstract: Power conservation in a phase locked loop (PLL) places the PLL into a low-power mode and periodically reactivates the PLL to prevent leakage current from causing a voltage controlled oscillator (VCO) within the PLL to drift. The PLL also includes an adjustable delay circuit positioned between an output of the VCO and an input of a phase detector, where the delay circuit is used to adjust phase slew of a feedback signal to help the PLL settle into a desired frequency. By controlling the drift of the VCO and keeping the phase slew of the feedback signal to a minimum, the PLL may be activated and settle to a desired frequency within a relatively short amount of time. By keeping this time so short, the PLL may be placed into and pulled out of a low-power mode and still meet rigid timing requirements of various transmission protocols.

Abstract: A method for offset calibration of a voltage comparator is disclosed according to certain aspects of the present disclosure. The method includes applying a first bias voltage to a gate of a first compensation transistor, wherein the first compensation transistor is coupled in series with a first input transistor of the voltage comparator. The method also includes applying a second bias voltage to a gate of a second compensation transistor, wherein the second compensation transistor is coupled in series with a second input transistor of the voltage comparator. The method further includes sensing a logic value at an output of the voltage comparator, and adjusting the first bias voltage and the second bias voltage based on the sensed logic value.

Abstract: Low latency transmission systems and methods for long distances in SOUNDWIRE systems are disclosed. In an exemplary aspect, a SOUNDWIRE sub-system is coupled to a long cable through a bridge. The bridge converts SOUNDWIRE signals to signals for transmission over the long cable and converts the signals from the long cable to the SOUNDWIRE signals for transmission in the SOUNDWIRE sub-system. Conversion between signal types may include concatenating signals of a similar type into a group that is serially transmitted over the long cable. Concatenation of bit slots in this manner consumes minimal overhead in bus turnaround, thereby reducing latency. In further aspects, the functionality of the bridge may be incorporated into a headset or a mobile terminal.

Abstract: A method for offset calibration of a voltage comparator is disclosed according to certain aspects of the present disclosure. The method includes applying a first bias voltage to a gate of a first compensation transistor, wherein the first compensation transistor is coupled in series with a first input transistor of the voltage comparator. The method also includes applying a second bias voltage to a gate of a second compensation transistor, wherein the second compensation transistor is coupled in series with a second input transistor of the voltage comparator. The method further includes sensing a logic value at an output of the voltage comparator, and adjusting the first bias voltage and the second bias voltage based on the sensed logic value.

Abstract: Apparatuses, methods, and systems for enabling higher current charging of Universal Serial Bus (USB) Specification Revision 2.0 (USB 2.0) portable electronic devices from USB 3.x hosts are disclosed. In one aspect, a USB 2.0 controller is provided in a USB 2.0 portable device. A USB 3.x controller is provided in a USB 3.x host. The USB 2.0 controller is configured to draw a higher charging current than specified in USB 2.0 for the USB 2.0 portable device over a USB 2.0 cable. In order to draw the higher charging current without violating USB 2.0, the USB 2.0 controller is configured to use one or more reserved elements in an existing USB 2.0 descriptor(s) or bitmap(s) to indicate a higher charging current request from the USB 2.0 controller.

Abstract: In certain aspects, a regulator includes a variable-impedance switch coupled between a supply rail and a circuit block, wherein the variable-impedance switch has an adjustable impedance. The regulator also includes a voltage level comparator configured to compare a block voltage at the circuit block with a reference voltage, and to output a first signal indicating whether the block voltage is higher or lower than the reference voltage based on the comparison. The regulator also includes a slope detector configured to determine whether the block voltage is rising or falling, and to output a second signal indicating whether the block voltage is rising or falling based on the determination. The regulator further includes a controller configured to receive the first signal and the second signal, and to control the impedance of the variable-impedance switch based on the first signal and the second signal.

Abstract: Two super-speed lanes may be enabled on a single USB cable. In an exemplary, non-limiting aspect, the USB cable is a Type-C cable. In further non-limiting aspects, the super-speed lanes may be present even if there is no USB 2.0 lane present on the D+/D? pins of the USB cable. Use of the second super-speed lane increases data throughput. Eliminating the requirement that the D+/D? pins be used for USB 2.0 data allows greater flexibility in the use of the USB connection because audio or video data may be sent over the D+/D? pins instead of USB 2.0 data. Further, the use of the two super-speed lanes allows a single computing element to operate as a host on one lane and a device on a second lane.

Abstract: Low latency transmission systems and methods for long distances in SOUNDWIRE systems are disclosed. In an exemplary aspect, a SOUNDWIRE sub-system is coupled to a long cable through a bridge. The bridge converts SOUNDWIRE signals to signals for transmission over the long cable and converts the signals from the long cable to the SOUNDWIRE signals for transmission in the SOUNDWIRE sub-system. Conversion between signal types may include concatenating signals of a similar type into a group that is serially transmitted over the long cable. Concatenation of bit slots in this manner consumes minimal overhead in bus turnaround, thereby reducing latency. In further aspects, the functionality of the bridge may be incorporated into a headset or a mobile terminal.

Abstract: A link layer to physical layer (PHY) serial interface is disclosed. In one aspect, a system on a chip (SoC) integrated circuit (IC) includes a link layer circuit, and a remote IC includes a Universal Serial Bus (USB) PHY circuit. A bus having four or fewer wires connects the two ICs. A link bridge communicates with the link layer circuit and serializes USB Transceiver Macrocell Interface (UTMI) signaling received from the link layer circuit as high speed (HS) USB messages for transmission to the remote IC. The link bridge also receives HS messages from the USB PHY circuit on the remote IC. The link bridge deserializes the HS messages to extract UTMI signaling and passes the extracted UTMI signaling to the link layer circuit.

Abstract: Low latency transmission systems and methods for long distances in SOUNDWIRE systems are disclosed. In an exemplary aspect, a SOUNDWIRE sub-system is coupled to a long cable through a bridge. The bridge converts SOUNDWIRE signals to signals for transmission over the long cable and converts the signals from the long cable to the SOUNDWIRE signals for transmission in the SOUNDWIRE sub-system. Conversion between signal types may include concatenating signals of a similar type into a group that is serially transmitted over the long cable. Concatenation of bit slots in this manner consumes minimal overhead in bus turnaround, thereby reducing latency. In further aspects, the functionality of the bridge may be incorporated into a headset or a mobile terminal.

Abstract: In certain aspects, a regulator includes a variable-impedance switch coupled between a supply rail and a circuit block, wherein an impedance of the variable-impedance switch is set by an impedance code input to the variable-impedance switch. The regulator also includes an analog-to-digital converter (ADC) configured to convert a block supply voltage at the circuit block into a voltage code, and a controller configured to adjust the impedance code based on the voltage code in a direction that reduces a difference between the block supply voltage and a target supply voltage.

Abstract: A method of triggering a desired operating mode in a universal serial bus (USB)-compatible client device is provided. A USB-compatible client device detects that it has been coupled to a USB-compatible host device via a USB bus. The USB-compatible client device attempts to pull a data line of the USB bus high. The USB-compatible client device then ascertains that the data line remains pulled low, thereby indicating that the USB-compatible client device should enter a first mode of operation. The USB-compatible client device operates according to the first mode of operation.

Abstract: Embedded Universal Serial Bus (USB) debug (EUD) for multi-interfaced debugging in electronic systems are disclosed. Electronic systems contain complex integrated circuits (ICs) that require extensive testing and debugging to ensure good quality and performance. In exemplary aspects, an EUD is provided in an electronic system. The EUD is configured to send control information to and/or collect debugging information from multiple internal debugging interfaces in the electronic system. The EUD is also configured to convert the debugging information into a USB format so that the debugging information can be externally accessed through a USB interface provided by the electronic system. The EUD can provide non-invasive monitoring of the electronic system. The electronic system is able to use a USB port for communications in a mission mode while EUD is enabled. Additionally, the electronic system can turn on or off all system clocks during power-saving mode while the EUD continues to function.

Abstract: Techniques for increased data flow in Universal Serial Bus (USB) cables are disclosed. In one aspect, two super-speed lanes may be enabled on a single USB cable. In an exemplary, non-limiting aspect, the USB cable is a Type-C cable. In further non-limiting aspects, the super-speed lanes may be present even if there is no USB 2.0 lane present on the D+/D? pins of the USB cable. Use of the second super-speed lane increases data throughput. Eliminating the requirement that the D+/D? pins be used for USB 2.0 data allows greater flexibility in the use of the USB connection because audio or video data may be sent over the D+/D? pins instead of USB 2.0 data. Further, the use of the two super-speed lanes allows a single computing element to operate as a host on one lane and a device on a second lane.

Abstract: Low latency transmission systems and methods for long distances in SOUNDWIRE systems are disclosed. In an exemplary aspect, a SOUNDWIRE sub-system is coupled to a long cable through a bridge. The bridge converts SOUNDWIRE signals to signals for transmission over the long cable and converts the signals from the long cable to the SOUNDWIRE signals for transmission in the SOUNDWIRE sub-system. Conversion between signal types may include concatenating signals of a similar type into a group that is serially transmitted over the long cable. Concatenation of bit slots in this manner consumes minimal overhead in bus turnaround, thereby reducing latency. In further aspects, the functionality of the bridge may be incorporated into a headset or a mobile terminal.

Abstract: Electronic devices are adapted to facilitate detection of a type of USB charger to which an electronic device is connected. According to one example, an electronic device can apply a current source to a data line of a USB plug coupled to a USB port. A determination can be made whether the data line has gone to a LOW state or remained at a HIGH state after a predetermined period of time. If the data line has gone to a LOW state, the USB port may be identified as a downstream port, such as a standard downstream port (SDP) or a charging downstream port (CDP). If the data line has remained at the HIGH state, the USB port may be identified as a dedicated charging port (DCP), no matter if it is compliant or non-compliant with the BC 1.2 spec. Other aspects, embodiments, and features are also included.

Abstract: Apparatuses and methods to distinguish proprietary, non-floating and floating chargers for regulating charging current are disclosed. In one aspect, a charger detection circuit is provided in a portable electronic device. The charger detection circuit is configured to detect whether a connected Universal Serial Bus (USB) charger is compliant with a USB battery charging specification. If the connected USB charger is non-compliant with the USB battery charging specification, the charger detection circuit is configured to further detect if the non-complaint USB charger is a non-compliant floating USB charger or a non-compliant proprietary USB charger. If the connected USB charger is determined to be a non-compliant proprietary USB charger, the portable electronic device can be configured to draw up to a maximum charging current according to the USB battery charging specification.

Abstract: A method of triggering a desired operating mode in a universal serial bus (USB)-compatible client device is provided. A USB-compatible client device detects that it has been coupled to a USB-compatible host device via a USB bus. The USB-compatible client device attempts to pull a data line of the USB bus high. The USB-compatible client device then ascertains that the data line remains pulled low, thereby indicating that the USB-compatible client device should enter a first mode of operation. The USB-compatible client device operates according to the first mode of operation.

Abstract: Apparatuses and methods to distinguish proprietary, non-floating and floating chargers for regulating charging current are disclosed. In one aspect, a charger detection circuit is provided in a portable electronic device. The charger detection circuit is configured to detect whether a connected Universal Serial Bus (USB) charger is compliant with a USB battery charging specification. If the connected USB charger is non-compliant with the USB battery charging specification, the charger detection circuit is configured to further detect if the non-complaint USB charger is a non-compliant floating USB charger or a non-compliant proprietary USB charger. If the connected USB charger is determined to be a non-compliant proprietary USB charger, the portable electronic device can be configured to draw up to a maximum charging current according to the USB battery charging specification.