Abstract: Significant performance improvements can be realized in data processing systems by confining the operation of a processor within its internal register file so as to reduce the instruction count executed by the processor. Data, which is sufficiently small enough to fit within the internal register file, can be transferred into the internal register file, and execution results can be removed therefrom, using direct memory accesses that are independent of the processor, thus enabling the processor to avoid execution of load and store instructions to manipulate externally stored data. Further, the data and execution results of the processing activity are also accessed and manipulated by the processor entirely within the internal register file. The reduction in instruction count, coupled with the standardization of multiple processors and their instruction sets, enables the realization of a highly scaleable, high-performing symmetrical multi-processing system at manageable complexity and cost levels.

Abstract: Packets received by a network device such as a switch are queued to either a multicast or unicast queue depending on whether a valid mapping of the packet destination address to an output port of the device exists. Each queued packet is marked with a service era during which the message is queued. The service era is advanced whenever a port mapping for a destination address becomes established and the multicast queue is non-empty. The device monitors the presence of packets on the multicast queue and the transfer of packets from the multicast queue to the output ports. A message is forwarded from the unicast queue to an output port only if the multicast queue was empty at the time the mapping was established, or if all messages on the multicast queue from service eras earlier than the service era of the message on the unicast queue have been transferred to the output port.

Abstract: Significant performance improvements can be realized in data processing systems by confining the operation of a processor within its internal register file so as to reduce the instruction count executed by the processor. Data, which is sufficiently small enough to fit within the internal register file, can be transferred into the internal register file, and execution results can be removed therefrom, using direct memory accesses that are independent of the processor, thus enabling the processor to avoid execution of load and store instructions to manipulate externally stored data. Further, the data and execution results of the processing activity are also accessed and manipulated by the processor entirely within the internal register file. The reduction in instruction count, coupled with the standardization of multiple processors and their instruction sets, enables the realization of a highly scaleable, high-performing symmetrical multi-processing system at manageable complexity and cost levels.

Abstract: Manual insertion of hardware jumpers to configure I/O device selection and addressing is eliminated through the implementation of specialized hardware which allows for program control over several addressing paths. A register file is utilized within a programmable device to configure demultiplexers and multiplexers which map I/O address control line signals to set up various communication paths for address I/O exchanges. I/O configuration is entirely removed from add-on cards through the use of the programmable device. Accordingly, such add-on cards only require minimum circuitry, thus facilitating the use of miniature or baby cards as option cards which are much smaller than standard add-on cards.