Abstract: A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.

Abstract: The present invention, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160 over a substrate 115, subjecting the first gate dielectric layer 160 to a first nitridation process, forming a second gate dielectric layer 165 over the substrate 115 and having a thickness less than a thickness of the first gate dielectric layer 160, and subjecting the first and second gate dielectric layers 160, 165 to a second nitridation process, wherein the first and second nitridation processes are different. The present invention also provides a microelectronics device 100 fabricated in accordance with the method.

Abstract: The present invention, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160 over a substrate 115, subjecting the first gate dielectric layer 160 to a first nitridation process, forming a second gate dielectric layer 165 over the substrate 115 and having a thickness less than a thickness of the first gate dielectric layer 160, and subjecting the first and second gate dielectric layers 160,165 to a second nitridation process, wherein the first and second nitridation processes are different. The present invention also provides a microelectronics device 100 fabricated in accordance with the method.

Abstract: A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.

Abstract: A method is provided, the method comprising measuring at least one parameter characteristic of processing performed on a workpiece in a processing step, and modeling the at least one characteristic parameter measured using a correlation model. The method also comprises applying the correlation model to modify the processing performed in the processing step.

Abstract: A method is provided, the method comprising measuring at least one parameter characteristic of rapid thermal processing performed on a workpiece in a rapid thermal processing step, and modeling the at least one characteristic parameter measured using a first-principles radiation model. The method also comprises applying the first-principles radiation model to modify the rapid thermal processing performed in the rapid thermal processing step.

Abstract: A method for identifying faulty wafers includes processing a set of wafers in a tool; collecting tool state information during the processing of the set of wafers; generating a tool state information baseline; comparing the tool state information for each wafer to the tool state information baseline to identify any wafers with outlying tool state information; and designating a particular wafer in the set as suspect in response to identifying outlying tool state information for the particular wafer. A processing line includes a tool adapted to process a set of wafers, and a process controller.

Abstract: A method and apparatus for providing fault detection in an Advanced Process Control (APC) framework. A first interface receives operational state data of a processing tool related to the manufacture of a processing piece. The state data is sent from the first interface to a fault detection unit. A fault detection unit determines if a fault condition exists with the processing tool based upon the state data. A predetermined action is performed on the processing tool in response to the presence of a fault condition. In accordance with one embodiment, the predetermined action is to shutdown the processing tool so as to prevent further production of faulty wafers.

Abstract: The present invention provides for a method and an apparatus for fault model analysis in manufacturing tools. A sequence of semiconductor devices is processed through a manufacturing process. Production data resulting from the processing of the semiconductor devices is acquired. A fault model analysis is performed using the acquired production data.

Abstract: A metbod for perforning a wafer-less qualification of a processing tool includes creating a wafer-less qualification model for the processing tool. Qualification data is generated from the processing tool iiiring a wafer-less qualification process. The qualification data is compared with the wafer-less qualification model. The processig tool is determined to be operating in a predefined state based on the comparison of the qualification data with the wafer-less qualification model.

Abstract: A method is provided, the method comprising measuring at least one parameter characteristic of rapid thermal processing performed on a workpiece in a rapid thermal processing step, and modeling the at least one characteristic parameter measured using a first-principles radiation model. The method also comprises applying the first-principles radiation model to modify the rapid thermal processing performed in the rapid thermal processing step.

Abstract: A method is provided, the method comprising measuring at least one parameter characteristic of processing performed on a workpiece in a processing step, and modeling the at least one characteristic parameter measured using a correlation model. The method also comprises applying the correlation model to modify the processing performed in the processing step.

Abstract: A method is provided, the method comprising preheating a rapid thermal processing chamber according to a preheating recipe and processing a first plurality of workpieces in the rapid thermal processing chamber. The method also comprises performing first parameter measurements on first and second workpieces of the first plurality of workpieces, the first parameter measurements indicative of first processing differences between the first and second workpieces, and forming a first output signal corresponding to the first parameter measurements. The method further comprises adjusting the preheating recipe based on the first output signal and using the adjusted preheating recipe to preheat the rapid thermal processing chamber for processing a second plurality of workpieces in the rapid thermal processing chamber to reduce second processing differences between first and second workpieces of the second plurality of workpieces.

Abstract: Methods of optimizing a preheat recipe for rapid thermal processing workpieces are provided. In one aspect, a method of manufacturing is provided that includes preheating a rapid thermal processing chamber according to a preheating recipe and processing a first plurality of workpieces in the rapid thermal processing chamber. Parameter measurements are performed on a first workpiece and a second workpiece of the first plurality of workpieces. The parameter measurements are indicative of processing differences between the first and second workpieces. An output signal is formed corresponding to the parameter measurements and a control signal based on the output signal is used to adjust the preheating recipe for preheating the rapid thermal processing chamber for processing a second plurality of workpieces in the rapid thermal processing chamber to reduce processing differences between first and second workpieces of the second plurality of workpieces.