Patents by Inventor Terrence James Stewart

Terrence James Stewart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pseudo-random address generation mechanism that reduces address translation time
    Patent number: 5897662
    Abstract: It is known that virtual memory segments that are allocated together tend to be used together. With existing sequential address allocation mechanisms, this in turn means that programs tend to end up using the same set or sets of virtual segment addresses (i.e., in the same minitable or minitables), which, as mentioned, leads to increased address translation time because of clumping. The address allocation mechanism of the present invention reduces clumping by allocating virtual segment addresses in a pseudo-random order. This decreases the likelihood that virtual segment addresses that are allocated together end up in the same set or sets of virtual segment addresses within the address translation table.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: April 27, 1999
    Assignee: International Business Machines Corporation
    Inventors: Michael Joseph Corrigan, Sheldon Bernard Levenstein, Terrence James Stewart