Abstract: This embodiment provides apparatus and method for implementing a High Speed Link (HSL) such as the newly proposed ANSI High Performance Parallel Interface (HIPPI) standard on processors complexes like the IBM 3090 having a paging store with an independent bus. A high speed link adapter (HSLA) including input and output buffers and controls is coupled to the independent bus under program control. Program access to high speed link is obtained by an extension to the Page-in and Page-out instructions.

Abstract: A priority circuit handles requests by three components of a data processing system for access to several resources of the system that can be accessed one at a time on each operating cycle of the system. A logic circuit receives requests by the requesters and grants access to one requester on a priority basis. The logic circuit has means for establishing a particular priority sequence, and the priority circuit includes means for stepping the logic circuit through a cycle of different priority sequences. In a repeating cycle of these steps, each requester is given the highest priority at least once. In a specific embodiment, the stepping means is a counter and a cycle is called a counting cycle. The stepping means is responsive to a control code to establish a particular stepping sequence.

Abstract: A channel communicator CC has a storage array for holding an entry for each channel and for holding a busy vector and an interrupt vector that each have a bit for each channel. The CC is connected between the input bus and the output bus that connect the channels and an I/O processor IOP to processor main store. A message to the CC includes the ID of the channel that the message is to or from and the CC uses this ID as an address for accessing a channel entry or a bit in a vector. The message also carries a command that controls the CC to store a data portion of a message or to fetch a channel entry or a vector from the array and load it onto the output bus addressed to the IOP or to one of the channels. The command also controls addressing a particular one of the vectors. The CC also has means responsive to a command to perform a sequence of operations for testing the vectors and for testing fields of an entry in the array and for using the results of the test to control the execution of the command.

Abstract: Storage access requests are forwarded from plural input/output channels to shared main storage. An address word in each request designates the identity of the source channel (CHID) and "destination" address (of a doubleword space in storage relative to which one, two or four "data" words shall be transferred). EOT tag signal provides demarcation of requests and also uniquely identifies "1-wide" input (Store) requests. Quadword (QW) tag, presented with "4-wide" requests, enables the storage access system to use a single address in the request to locate two contiguous doubleword spaces in storage. Data tags (D1, D2), presented on a selective basis enable the access system to selectively steer (reorder the positions of) data words in an input request relative to word halves of the addressed space.

Abstract: The Channel Bus Controller (CBC) transfers information between groups of input/output channels and processor storage. Storage receives or dispenses two data words per access operation. Interfaces for transfers from the channel groups to the CBC are advantageously one word wide; since each output (fetch) request consists of a single request word. Information sent by each group is assembled into three-word units (a request word and zero, one or two data words) in a respective channel bus assembly register (CBAR). The assembled unit is passed from the CBAR to a respective area of an In Buffer array and from that array to storage. Zero filler words are inserted into unused data word positions. A channel request may be tagged to designate a transfer of four data words. If the transfer is an input the four data words are sent to the CBC with a single request word.