Abstract: A method of generating a customized secondary power distribution assembly (SPDA) includes generating one or more customizable SPDAs. Each of the one or more customizable SPDAs is a construct corresponding with a microprocessor configured to control a set of customizable channels in each of a set of virtual line replaceable modules (vLRMs). The method also includes creating a mapping between one of the one or more customizable SPDAs and the customized SPDA, the mapping indicating line replaceable modules (LRMs) of the customized SPDA and defining each channel of each LRM, and deploying the customized SPDA in an application. The microprocessor is initiated to control the customized SPDA according to the mapping at startup.

Abstract: A method of generating a customized secondary power distribution assembly (SPDA) includes generating one or more customizable SPDAs. Each of the one or more customizable SPDAs is a construct corresponding with a microprocessor configured to control a set of customizable channels in each of a set of virtual line replaceable modules (vLRMs). The method also includes creating a mapping between one of the one or more customizable SPDAs and the customized SPDA, the mapping indicating line replaceable modules (LRMs) of the customized SPDA and defining each channel of each LRM, and deploying the customized SPDA in an application. The microprocessor is initiated to control the customized SPDA according to the mapping at startup.

Abstract: An assembly for an aircraft according to an example of the present disclosure includes, among other things, a control module including a processor and a local memory that stores a first instance of operational software executable by the processor and that relates to functionality of the control module to selectively control a vehicle system, and a backplane memory device coupled to the control module by a common backplane. The backplane memory device includes shadow memory that stores a second instance of the operational software. A method of synchronizing an assembly is also disclosed.

Abstract: A power distribution assembly according to an example of the present disclosure includes, among other things, a housing at least partially receiving a plurality of hardware modules coupled to a backplane, the plurality of hardware modules including at least one output module and a communications module that communicates information between the plurality of hardware modules and a second power distribution assembly. At least one hardware module of the plurality of hardware modules includes a field programmable gate array that commands the at least one output module to selectively power at least one aircraft system. A method of operation of a power distribution system is also disclosed.

Abstract: An assembly for an aircraft according to an example of the present disclosure includes, among other things, a control module including a processor and a local memory that stores a first instance of operational software executable by the processor and that relates to functionality of the control module to selectively control a vehicle system, and a backplane memory device coupled to the control module by a common backplane. The backplane memory device includes shadow memory that stores a second instance of the operational software. A method of synchronizing an assembly is also disclosed.

Abstract: A power distribution assembly according to an example of the present disclosure includes, among other things, a housing at least partially receiving a plurality of hardware modules coupled to a backplane, the plurality of hardware modules including at least one output module and a communications module that communicates information between the plurality of hardware modules and a second power distribution assembly. At least one hardware module of the plurality of hardware modules includes a field programmable gate array that commands the at least one output module to selectively power at least one aircraft system. A method of operation of a power distribution system is also disclosed.

Abstract: A method and system to perform deterministic timing analysis of a plurality of software tasks involves cache memory that is shared by the plurality of software tasks. Real memory is accessible by the plurality of software tasks. A task scheduler establishes a cache flush between executions of consecutive tasks among the plurality of software tasks. The cache flush includes movement of data in the cache memory to the real memory. A processor executes the plurality of software tasks to obtain a worst case execution time (WCET) associated with each of the plurality of software tasks.

Abstract: A method for incorporating a set of requirements into an executable program to be run on an airborne system is provided. The method obtains the set of requirements for the program in a first format. The method uses a first tool to convert the set of requirements in the first format into a second format utilizing a markup language. The method uses a second tool to convert the set of requirements in the second format into a third format that influences a behavior of the program without changing the program. The method uses a third tool to determine whether the set of requirements in the third format incorporates all of the set of requirements in the second format in order to verify the program under a compliance standard for the airborne system without performing a verification process directly on the program.