Patents by Inventor Terrence Stewart

Terrence Stewart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12014263
    Abstract: The present invention relates to methods and systems for encoding and processing representations that include continuous structures using vector-symbolic representations. The system is comprised of a plurality of binding subsystems that implement a fractional binding operation, a plurality of unbinding subsystems that implement a fractional unbinding operation, and at least one input symbol representation that propagates activity through a binding subsystem and an unbinding subsystem to produce a high-dimensional vector representation of a continuous space.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: June 18, 2024
    Assignee: APPLIED BRAIN RESEARCH INC.
    Inventors: Aaron Russell Voelker, Christopher David Eliasmith, Brent Komer, Terrence Stewart
  • Publication number: 20200302281
    Abstract: The present invention relates to methods and systems for encoding and processing representations that include continuous structures using vector-symbolic representations. The system is comprised of a plurality of binding subsystems that implement a fractional binding operation, a plurality of unbinding subsystems that implement a fractional unbinding operation, and at least one input symbol representation that propagates activity through a binding subsystem and an unbinding subsystem to produce a high-dimensional vector representation of a continuous space.
    Type: Application
    Filed: March 18, 2020
    Publication date: September 24, 2020
    Inventors: Aaron Russell VOELKER, Christopher David ELIASMITH, Brent KOMER, Terrence STEWART
  • Publication number: 20200019839
    Abstract: Methods and apparatus for spiking neural network computing based on e.g., a multi-layer kernel architecture, shared dendritic encoding, and/or thresholding of accumulated spiking signals. In one embodiment, a thresholding accumulator is disclosed that reduces spiking activity between different stages of a neuromorphic processor. Spiking activity can be directly related to power consumption and signal-to-noise ratio (SNR); thus, various embodiments trade-off the costs and benefits associated with threshold accumulation. For example, reducing spiking activity (e.g., by a factor of 10) during an encoding stage can have minimal impact on downstream fidelity (SNR) for a decoding stage, while yielding substantial improvements in power consumption.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 16, 2020
    Inventors: Kwabena Adu Boahen, Sam Brian Fok, Alexander Smith Neckar, Ben Varkey Benjamin Pottayil, Terrence Stewart, Nick Nirmal Oza, Rajit Manohar, Christopher David Eliasmith