Abstract: Nickel salicide processing is implemented by forming a non-stoicheiometric mediating layer, such as ozonated SiOx, to control the reaction of Ni and Si during annealing to form a NiSi layer on the polysilicon gate electrodes and source/drain regions without conductive bridging between the metal silicide layer on the gate electrode and the metal silicide layers on associated source/drain regions. Embodiments of the present invention comprise forming silicon nitride sidewall spacers on the side surfaces of the gate electrode.

Abstract: An integrated circuit and method of manufacture therefore is provided having a semiconductor substrate with a semiconductor device with a dielectric layer over the semiconductor substrate. A conductor core fills the opening in the dielectric layer. An etch stop layer with a dielectric constant below 5.5 is formed over the first dielectric layer and conductor core. A second dielectric layer over the etch stop layer has an opening provided to the conductor core. A second conductor core fills the second opening and is connected to the first conductor core.

Abstract: A patterned metal layer is gap filled with HSQ, an oxide formed thereon by PECVD, e.g., silicon dioxide derived from silane and N.sub.2 O, and planarized. The dielectric constant of the HSQ layer is minimized by baking the deposited HSQ layer in an inert atmosphere, e.g., N.sub.2, before heat soaking in an N.sub.2 O-containing atmosphere for no more than about 10 seconds and subsequent PECVD.