Abstract: When an input digital signal, having a portion with an associated control value, is connected to a digital filter with adaptive compensation, the digital filter with adaptive compensation selects one of a plurality of coefficient scalers (9501, 9601) as directed by a control bus (990). As the input digital signal propagates through the filter, one of a plurality of next coefficient scalers (9502,9602) are selected by the control bus (990). The digital filter with adaptive compensation interleaves in time the coefficients of multiple conventional filters in order to filter each portion of the digital signal according to its associated control value.

Abstract: In a digital modulator with compensation, a digital bit stream from a microphone (705), a speech coder (706), and a channel encoder (707) is sent to an encoder (720) which translates the bits into I/Q digital pulses with phase shift keying. A symbol correlater (730) notes when predetermined target phase symbol sequences, which contribute to a high peak-to-average power ratio, enter the encoder. If a target symbol sequence is encountered, the correlater directs compensation amplifiers or compensation filters (734, 737) of the I/Q signals. Next, I/Q pulse shaping filters (764, 765) filter the I/Q pulses according to communication system specifications. The filtered I/Q signals are then sent to a quadrature modulator (790) for RF modulation. Compensation of target symbol sequences reduces the negative impact they have on peak-to-average power ratio and increases the efficiency of the power amplifier (795) which extends the battery life of a communication device (700).

Abstract: An error detector circuit and associated method for a digital receiver. The digital receiver is operative in a TDMA communication scheme in which DQPSK-modulated signals are generated, such as the Japanese Digital Cordless Telephone System. The error detector circuit detects times in which an excessive amount of noise or other distortion is introduced upon one or more sequences of a signal transmitted during one or more time slots in the TDMA communications scheme. A receiver incorporating the error detector circuit is operative not to decode portions of a received signal when excessive numbers of sequences include excessive amounts of noise or other distortion introduced thereupon. Thereby, degradation of the audio quality of a signal actually recreated by the receiver incorporating the error detector.

Abstract: A power saving arrangement for a microcomputer having a first clock signal operating at a predetermined frequency employs a reduced clock frequency to peripheral circuitry to limit power consumption during a disable or halt mode. A control circuit disables a clock signal provided to the microcomputer, while a clock divider divides the predetermined frequency to generate a reduced frequency signal upon which the peripheral circuitry may operate. After receiving an external wake-up signal, the peripheral circuitry interrupts the microcomputer in order to revert the microcomputer back to normal operation.