Patents by Inventor Terry C Huang

Terry C Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Shared mesh
    Patent number: 10193826
    Abstract: A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: January 29, 2019
    Assignee: INTEL CORPORATION
    Inventors: Bahaa Fahim, Yen-Cheng Liu, Chung-Chi Wang, Donald C. Soltis, Jr., Terry C. Huang, Tejpal Singh, Bongjin Jung, Nazar Syed Haider
  • SHARED MESH
    Publication number: 20170019350
    Abstract: A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.
    Type: Application
    Filed: July 15, 2015
    Publication date: January 19, 2017
    Inventors: Bahaa Fahim, Yen-Cheng Liu, Chung-Chi Wang, Donald C. Soltis, JR., Terry C. Huang, Tejpal Singh, Bongjin Jung, Nazar Syed Haider
  • Apparatus and method for performing speculative cache directory tag updates
    Patent number: 6564306
    Abstract: An apparatus and method for performing speculative directory cache tag updates for read accesses to memory is herein disclosed. A control unit for performing tag updates is coupled between the memory controller and the memory bank in a multiprocessor system that employs a directory-based coherency protocol. The control unit transmits data read from the memory bank to the memory controller while calculating the updated tag that it then writes back to the memory bank. In this manner, the memory bank busy time and memory bus traffic are reduced thereby improving the overall performance of a memory access.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: May 13, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael K Dugan, Gary B Gostin, Mark A Heap, Terry C Huang, Curtis R. McAllister, Henry Yu
  • Apparatus and method for performing speculative cache directory tag updates
    Publication number: 20010034815
    Abstract: An apparatus and method for performing speculative directory cache tag updates for read accesses to memory is herein disclosed. A control unit for performing tag updates is coupled between the memory controller and the memory bank in a multiprocessor system that employs a directory-based coherency protocol. The control unit transmits data read from the memory bank to the memory controller while calculating the updated tag that it then writes back to the memory bank. In this manner, the memory bank busy time and memory bus traffic are reduced thereby improving the overall performance of a memory access.
    Type: Application
    Filed: February 28, 2001
    Publication date: October 25, 2001
    Inventors: Michael K. Dugan, Gary B. Gostin, Mark A. Heap, Terry C. Huang, Curtis R. McAllister, Henry Yu