Abstract: The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The circuit of the present invention replaces the typical scheme of power supply sequencing to fix the problem. The circuit disclosed herein detects the state of the core voltage and disables the output drivers when the core voltage is detected as being off. The disabled drivers are put into a high impedance state, thereby eliminating the potential for damage and eliminating the need for power supply sequencing. The invention also protects against the sudden loss of the integrated circuit core voltage, VDD, power supply during normal operation.

Abstract: A latched receiver circuit capable of receiving data and clock simultaneously. New data is latched at every clock cycle without delay or buffering of the data or the clock. The latched receiver may also receive and latch small signals without the aid of a receiver preamp or added delay.