Abstract: A method and a circuit for testing an integrated circuit are disclosed. In one embodiment, a self-resetting dynamic circuit, also known as a fireball circuit, contains a scan circuit and at least one Set Dominant Latches (“SDL”) where each SDL includes a keeper node. When scan clock is active, the scan data propagates from the scan circuit to the self-resetting dynamic circuit through the keeper node.

Abstract: A method and apparatus provides an efficient ratioed digital logic structure. The digital logic structure includes ratioed pull-up transistors and pull-down transistors such that the circuit noise margin does not substantially affect gain performance of the ratio stage. In one particular embodiment, a ratioed logic structure includes PMOS transistors and NMOS transistors that receive input voltage signals wherein a current path is induced in the NMOS transistors when a voltage input of zero or less is applied. Another feature of the present invention allows modification of gain performance of the ratio stage by arranging different ratios of the PMOS-to-NMOS transistor channel widths.

Abstract: An embodiment of the present invention includes a switchable conductive pathway between a number of intermediate nodes in a domino stage, up to and including every intermediate node, and a voltage source. In operation, this circuit configuration prevents the problems associated with charge sharing. The voltage, at the voltage source which is coupled to the intermediate nodes, is substantially equal to the voltage at a voltage source that is coupled by way of a domino precharge circuit to the output node of the domino stage. The switchable conductive pathways are switched on at the start of the precharge phase, and switched off at the beginning of the evaluation phase. In this way, intermediate node voltages in a domino stage are actively maintained, even after the main precharge control signal has been deasserted. Active maintenance of the intermediate nodes is suspended during the evaluation phase.

Abstract: A pulse generating circuit includes a first pulse generating circuit for generating a first output pulse, and a second pulse generating circuit for outputting a second output pulse. Each pulse generating circuit comprises a stack of two n-channel transistors and a reset circuit. The reset circuit includes two p-channel transistors and two inverters and is provided for automatically resetting the pulse generating circuits. The second pulse generating circuit includes a delay element for introducing an additional gate delay in the generation of the second output pulse. The additional gate delay introduces an asymmetry in the output pulses which offsets or cancels a previously introduced asymmetry of an input clock signal to generate an output clock signal having a constant period. Clock gating circuitry is provided for selectively enabling and disabling at least one of said pulse generator circuits.