Patents by Inventor Terry E. Burnette

Terry E. Burnette has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7074627
    Abstract: A solder system includes a lead (Pb) indicator and a solder flux. A method for forming a semiconductor device includes providing a carrier, applying the solder system to the carrier, coupling the terminal to the carrier via the solder system, melting the solder system to attach the terminal to the carrier and form a completed semiconductor device, and determining if the completed semiconductor device has a different predetermined property from the solder system.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: July 11, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Terry E. Burnette, Thomas H. Koschmieder
  • Patent number: 7067907
    Abstract: Improved electro-mechanical connections between a packaged semiconductor die (12) and a printed circuit board (60) with reduced standoff height and pitch are created by the use of a non-planar semiconductor package substrate (24) having a surface with angulated portions. Electrically conductive surfaces (54) are formed over the angulated portions. In one embodiment, the electrically conductive surfaces may be formed by forming an electrically conductive surface (54) over a non-planar or angulated package substrate (42). The electrically conductive angulated surfaces improve reliability of solder joints (70) upon connecting the packaged semiconductor die to the printed circuit board (60). The gaps within the solder mask openings provide a thin profile and improved pitch. In one form, the die may be on a same side of the package as the angulated substrate surface.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: June 27, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas H. Koschmieder, Terry E. Burnette
  • Publication number: 20040188812
    Abstract: Improved electro-mechanical connections between a packaged semiconductor die (12) and a printed circuit board (60) with reduced standoff height and pitch are created by the use of a non-planar semiconductor package substrate (24) having a surface with angulated portions. Electrically conductive surfaces (54) are formed over the angulated portions. In one embodiment, the electrically conductive surfaces may be formed by forming an electrically conductive surface (54) over a non-planar or angulated package substrate (42). The electrically conductive angulated surfaces improve reliability of solder joints (70) upon connecting the packaged semiconductor die to the printed circuit board (60). The gaps within the solder mask openings provide a thin profile and improved pitch. In one form, the die may be on a same side of the package as the angulated substrate surface.
    Type: Application
    Filed: March 27, 2003
    Publication date: September 30, 2004
    Inventors: Thomas H. Koschmieder, Terry E. Burnette
  • Publication number: 20030102535
    Abstract: A semiconductor device (50) includes a semiconductor die (52) having electronic circuitry that is connected to a substrate (54). The substrate (54) is used to interface the semiconductor die (52) to a printed circuit board (64). The substrate (54) includes a plurality of bonding pads (56, 58). A first portion of the plurality of bonding pads are soldermask defined (SMD) bonding pads (56) and a second portion of the plurality of bonding pads are non-soldermask defined (NSMD) bonding pads (58). Using a combination of SMD and NSMD bonding pads provides the advantages of good thermal cycling reliability and good bending reliability over devices that have only SMD bonding pads or NSMD bonding pads.
    Type: Application
    Filed: January 15, 2003
    Publication date: June 5, 2003
    Inventors: Terry E. Burnette, Thomas H. Koschmieder, Andrew J. Mawer
  • Patent number: 6552436
    Abstract: A semiconductor device (50) includes a semiconductor die (52) having electronic circuitry that is connected to a substrate (54). The substrate (54) is used to interface the semiconductor die (52) to a printed circuit board (64). The substrate (54) includes a plurality of bonding pads (56, 58). A first portion of the plurality of bonding pads are soldermask defined (SMD) bonding pads (56) and a second portion of the plurality of bonding pads are non-soldermask defined (NSMD) bonding pads (58). Using a combination of SMD and NSMD bonding pads provides the advantages of good thermal cycling reliability and good bending reliability over devices that have only SMD bonding pads or NSMD bonding pads.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: April 22, 2003
    Assignee: Motorola, Inc.
    Inventors: Terry E. Burnette, Thomas H. Koschmieder, Andrew J. Mawer
  • Publication number: 20020070451
    Abstract: A semiconductor device (50) includes a semiconductor die (52) having electronic circuitry that is connected to a substrate (54). The substrate (54) is used to interface the semiconductor die (52) to a printed circuit board (64). The substrate (54) includes a plurality of bonding pads (56, 58). A first portion of the plurality of bonding pads are soldermask defined (SMD) bonding pads (56) and a second portion of the plurality of bonding pads are non-soldermask defined (NSMD) bonding pads (58). Using a combination of SMD and NSMD bonding pads provides the advantages of good thermal cycling reliability and good bending reliability over devices that have only SMD bonding pads or NSMD bonding pads.
    Type: Application
    Filed: December 8, 2000
    Publication date: June 13, 2002
    Inventors: Terry E. Burnette, Thomas H. Koschmieder, Andrew J. Mawer