Abstract: A tamper detection system for a control module of a vehicle comprises first nonvolatile memory that stores N rewriteable components including at least one of calibration and software that is used to operate a controlled device of the vehicle, wherein N is an integer greater than zero. The N rewriteable components include an embedded part number (EPN) and an embedded verification number (EVN). Second nonvolatile memory includes a history buffer. A tampering detection module includes a calculated verification number (CVN) generator that generates a CVN for at least one of the N rewriteable components and that stores the CVN in the history buffer. A locking module selectively locks the history buffer under certain conditions.

Abstract: A tamper detection system for a control module of a vehicle comprises first nonvolatile memory that stores N rewriteable components including at least one of calibration and software that is used to operate a controlled device of the vehicle, wherein N is an integer greater than zero. The N rewriteable components include an embedded part number (EPN) and an embedded verification number (EVN). Second nonvolatile memory includes a history buffer. A tampering detection module includes a calculated verification number (CVN) generator that generates a CVN for at least one of the N rewriteable components and that stores the CVN in the history buffer. A locking module selectively locks the history buffer under certain conditions.

Abstract: An integrated circuit microprocessor (30) reads data from an external memory device (22, 23) through early overlapping memory access cycles, thus allowing efficient accesses to slower-speed memory. The microprocessor (30) drives a first address and activates a chip enable signal during a first clock period. The chip enable signal causes the external memory device to latch the first address and begin a first memory access. During a second, subsequent clock period, the microprocessor (30) provides a second address and again activates the chip enable signal. During a third clock period, subsequent to the second clock period, the microprocessor (30) latches a first data element associated with the first address. This early overlapping memory access type allows a memory device with a slow memory core to pipeline the second access prior to completion of the first access, increasing system efficiency.