Patents by Inventor Terry F. Ritter

Terry F. Ritter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5727062
    Abstract: Data blocks of various size can be processed in fast, effective block cipher mechanisms. Variable size confusion layers and variable size diffusion layers combine to form variable size block ciphers. Block size can set (typically byte-by-byte) at design time or dynamically during operation.The embodiment of FIG. 1 consists of horizontal layers alternating between confusion and diffusion. Here, each confusion layer, such as the layer including byte-wide substitution operation (16), uses keyed substitution tables which are initialized prior to operation. Simple and fast diffusion layers, such as the layer including byte-wide exclusive-OR (20), generally diffuse in just one direction. Consequently, multiple diffusion layers are usually required, such as those including byte-wide exclusive-OR operations (28) and (36). This kind of diffusion is unusual in a block cipher because it is extremely weak.
    Type: Grant
    Filed: July 6, 1995
    Date of Patent: March 10, 1998
    Inventor: Terry F. Ritter
  • Patent number: 5623549
    Abstract: An enhanced cryptographic mechanism employs Latin square derived balanced size-preserving block mixers and strong, practical fencing arrays of substitution mechanisms in combination with each other and with block ciphers. Ciphers are expanded into efficient, larger, stronger versions. Block ciphers, in combination with balanced block mixers and/or with substitution mechanisms, produce cryptographic mechanisms with block sizes that are combinations of the sizes of the block ciphers. Ciphers using large data blocks can reduce data expansion to levels normally consistent with small blocks. Different sized enhanced cryptographic mechanisms are used in a multiple-size cryptographic mechanism to minimize wasted block space in a ciphered message. The cryptographic mechanism provides at least three layers of processing.
    Type: Grant
    Filed: January 30, 1995
    Date of Patent: April 22, 1997
    Inventor: Terry F. Ritter
  • Patent number: 4979832
    Abstract: A first data source and a second data source are combined into a complex intermediate form or result; the first data source can be extracted from the intermediate form using the second data source. The combining mechanism can provide an alternative to the exclusive-OR combiner commonly used in stream ciphers.Each data value from the first data source is transformed by substitution using one of potentially multiple translation tables (12). The translations within each table can be changed after each substitution operation using a changes controller (18). Commonly, the just-used table is re-arranged or permuted; permutation retains invertibility, so that the ciphertext may be deciphered. As a particular design, the just-used substitution element may be exchanged with some element within the same table, as selected by the second data source, after every translation.
    Type: Grant
    Filed: November 1, 1989
    Date of Patent: December 25, 1990
    Inventor: Terry F. Ritter
  • Patent number: 4344133
    Abstract: A digital processor capable of responding to a sync instruction for high-speed synchronization of hardware and software is provided. The sync instruction places the procesor in a stopped state and lets the processor start up again only upon receipt of an interrupt. If the interrupt is disabled by being masked, the stopped state is simply cleared and the sequencing of instructions continues without vectoring to the interrupt service routine. However if the interrupt is not disabled, the processor will handle the interrupt just as it would if it were not in the stopped state. Upon return from the interrupt service routine, the stopped state is cleared and the sequencing of instructions continues. In this way, the sync instruction provides a mechanism for synchronizing software with hardware external to the processor without the delays associated with interrupts or busy-wait loops.
    Type: Grant
    Filed: April 14, 1980
    Date of Patent: August 10, 1982
    Assignee: Motorola, Inc.
    Inventors: William C. Bruce, Jr., Fuad H. Musa, Terry F. Ritter
  • Patent number: 4250546
    Abstract: A method of performing a fast interrupt in a digital data processor having the capability of handling more than one interrupt is provided. When a fast interrupt request is received a flag is set and the program counter and condition code registers are stored on a stack. At the end of the interrupt servicing routine the return from interrupt instructions retrieves the condition code register which contains the status of the digital data processor and checks to see whether the flag has been set or not. If the flag is set it indicates that a fast interrupt was serviced and therefore only the program counter is unstacked.
    Type: Grant
    Filed: July 31, 1978
    Date of Patent: February 10, 1981
    Assignee: Motorola, Inc.
    Inventors: Joel F. Boney, Fuad H. Musa, Terry F. Ritter