Abstract: A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.

Abstract: The present invention provides a method for etching a substrate in the manufacture of a semiconductor device, the method comprising contacting a surface of the substrate with ions extracted from a plasma formed from a gas comprising one or more of an oxygen-containing species, a nitrogen-containing species and an inert gas, and separately contacting the surface of the substrate with a plasma formed from a gas comprising a fluorine-containing species.

Abstract: A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.

Abstract: A method for forming a conductive via is discussed and includes forming a seed layer over a first side of a semiconductor substrate, wherein the semiconductor substrate includes a first side opposite a second side, forming a via hole in a semiconductor substrate from the second side of the semiconductor substrate, wherein the via hole exposes the seed layer; and electroplating a conductive via material in the via hole from the seed layer. In one embodiment, a continuous conductive layer is formed over and electrically coupled to the seed layer. The continuous conductive layer can serve as the current source while electroplating the conductive via material.

Abstract: A semiconductor fabrication method that includes forming a patterned mask (62, 72) by spin coating a developable hard mask layer (32) and a resist layer (42) over a semiconductor substrate (4). Subsequently, the resist layer (42) is exposed and developed to form a patterned resist layer (62), where the development step also removes the underlying hard mask layer (32), thereby forming a patterned mask (62, 72) which defines a void or printed feature to expose a region (97) over the semiconductor substrate which may be implanted, etched or otherwise processed.

Abstract: A method of forming a semiconductor device includes forming active circuitry over a semiconductor substrate, wherein the semiconductor substrate has a first major surface and a second major surface and the first active circuitry is formed over the first major surface of the semiconductor substrate. A via is formed within the first semiconductor substrate, wherein the via extends from the first active circuitry to the second major surface of the first semiconductor substrate. A dielectric layer is formed over the second major surface and adjacent the first via. The dielectric layer may include nitrogen and silicon and may be formed by a low pressure, low temperature, or both plasma process.

Abstract: A method for forming a conductive via is discussed and includes forming a seed layer over a first side of a semiconductor substrate, wherein the semiconductor substrate includes a first side opposite a second side, forming a via hole in a semiconductor substrate from the second side of the semiconductor substrate, wherein the via hole exposes the seed layer; and electroplating a conductive via material in the via hole from the seed layer. In one embodiment, a continuous conductive layer is formed over and electrically coupled to the seed layer. The continuous conductive layer can serve as the current source while electroplating the conductive via material.

Abstract: A method of forming a semiconductor device includes forming active circuitry over a semiconductor substrate, wherein the semiconductor substrate has a first major surface and a second major surface and the first active circuitry is formed over the first major surface of the semiconductor substrate. A via is formed within the first semiconductor substrate, wherein the via extends from the first active circuitry to the second major surface of the first semiconductor substrate. A dielectric layer is formed over the second major surface and adjacent the first via. The dielectric layer may include nitrogen and silicon and may be formed by a low pressure, low temperature, or both plasma process.

Abstract: A method for achieving a through-substrate via through a substrate having active circuitry on a first major surface begins by forming a hole into the substrate through the first major surface. The hole is lined with a conductive layer. A dielectric layer is deposited over the conductive layer. This deposition is performed in a manner that causes the dielectric layer to be substantially conformal. Conductive material is formed over first dielectric layer. A second major surface of the substrate is etched to expose the conductive material.

Abstract: Via holes to the source/drains of a transistor are made to have very uniform depths so that photoresist thickness can be minimized to reduce the problems associated with small hole vias and vias that are at minimum pitches. This is achieved by polishing a dielectric over the gate stack to a polish stop present over the gate stack to result in having a top surface that is coplanar with the top surface of the polish stop layer over the gate stack. This establishes a top surface that is very uniform in height above the substrate across the wafer. A subsequent dielectric formed on this top surface is thus also very uniform in height over the wafer. The photoresist thickness then can be selected to the least thickness necessary based upon the expectation of maintaining a pattern for etching through a layer of very uniform thickness.

Abstract: A method for forming a sacrificial layer (30) over patterned structures (28) to allow structures (28) to be trimmed laterally without incurring much loss vertically. Structures (28) are patterned on a first layer (26) of a substrate (24). Thereafter, sacrificial layer (30) is deposited on structures (28). During this deposition, the thickness of sacrificial layer (28) grows vertically above structures (28) faster than it grows laterally adjacent to the structures' sidewalls. Sacrificial layer (30) and patterned structures (28) are then etched where the etch rate uniformity ensures that the sacrificial layer (30) covering the sidewalls is cleared before the sacrificial layer covering the horizontal portions thereby enabling etching of the patterned structure sidewalls without reducing the patterned structure height. The sacrificial layer may comprise a polymer formed with a low energy fluorocarbon plasma while the subsequent etch may employ an oxygen plasma.

Abstract: A semiconductor fabrication method that includes forming a film (109) comprising an imaging layer (112) and an under layer (110) over a semiconductor substrate (102). The imaging layer (112) is patterned to produce a printed feature (116) having a printed dimension (124). The under layer (110) is then processed to produce a sloped sidewall void (120) in the under layer (110) wherein the void (120) has a finished dimension (126) in proximity to the underlying substrate that is less than the printed dimension. Processing the under layer (110) may include exposing the wafer to high density low pressure N2 plasma.

Abstract: Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.

Abstract: Via holes to the source/drains of a transistor are made to have very uniform depths so that photoresist thickness can be minimized to reduce the problems associated with small hole vias and vias that are at minimum pitches. This is achieved by polishing a dielectric over the gate stack to a polish stop present over the gate stack to result in having a top surface that is coplanar with the top surface of the polish stop layer over the gate stack. This establishes a top surface that is very uniform in height above the substrate across the wafer. A subsequent dielectric formed on this top surface is thus also very uniform in height over the wafer. The photoresist thickness then can be selected to the least thickness necessary based upon the expectation of maintaining a pattern for etching through a layer of very uniform thickness.

Abstract: A semiconductor fabrication method that includes forming a film (109) comprising an imaging layer (112) and an under layer (110) over a semiconductor substrate (102). The imaging layer (112) is patterned to produce a printed feature (116) having a printed dimension (124). The under layer (110) is then processed to produce a sloped sidewall void (120) in the under layer (110) wherein the void (120) has a finished dimension (126) in proximity to the underlying substrate that is less than the printed dimension. Processing the under layer (110) may include exposing the wafer to high density low pressure N2 plasma.

Abstract: Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.

Abstract: A method for forming a sacrificial layer (30) over patterned structures (28) to allow structures (28) to be trimmed laterally without incurring much loss vertically. Structures (28) are patterned on a first layer (26) of a substrate (24). Thereafter, sacrificial layer (30) is deposited on structures (28). During this deposition, the thickness of sacrificial layer (28) grows vertically above structures (28) faster than it grows laterally adjacent to the structures' sidewalls. Sacrificial layer (30) and patterned structures (28) are then etched where the etch rate uniformity ensures that the sacrificial layer (30) covering the sidewalls is cleared before the sacrificial layer covering the horizontal portions thereby enabling etching of the patterned structure sidewalls without reducing the patterned structure height. The sacrificial layer may comprise a polymer formed with a low energy fluorocarbon plasma while the subsequent etch may employ an oxygen plasma.

Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Abstract: A process for forming a semiconductor device includes placing a substrate (104) into an apparatus (300), creating a plasma, and processing the substrate (104). The apparatus (300) includes an electromagnetic source (120), a bulk material (302), and a first barrier layer (304). The bulk material (302) is between the electromagnetic source (120) and an interior (126) of the apparatus (300). The first barrier layer (304) is between the bulk material (302) and the interior (126). A process for operating an apparatus (300) includes forming a polymer layer along an inorganic layer (302, 306or 702), wherein the polymer layer is formed within the apparatus (300); removing the polymer layer to expose the inorganic layer (302, 306, or 702); and etching at least a portion of the exposed inorganic layer (302, 306, or 702). Typically, the inorganic layer (203, 306, or 702) is semiconductive or resistive.

Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.