Abstract: This application discloses a computing system to identify a stage of a logic pipeline described in a circuit design that, when implemented in configurable hardware, spans between partitions in the configurable hardware. The computing system can modify the circuit design to alter a timing for logic operations in the logic pipeline, which reduces slack in at least one stage in the logic pipeline adjacent to the identified stage in the logic pipeline. The computing system can utilize the slack reduced from at least one of the stages adjacent to the identified stage to increase a clock frequency in the configurable hardware or increase a time available for propagation delay associated with the identified stage. The computing system can generate a configuration for the configurable hardware that implements the logic pipeline with the altered timing in the configurable hardware.

Abstract: This application discloses an device disposed on a substrate, and a heat sink disposed on the substrate over the device. The heat sink disposed on the substrate forms a cavity to hold a fluid between the heat sink and the device. The fluid can absorb heat emitted by the device and transfer at least a portion of the absorbed heat to the heat sink. A gasket can be disposed between and in contact with the substrate and the heat sink. The gasket can prevent the fluid from exiting the cavity formed by the heat sink disposed on the substrate. The heat sink can have an opening to the cavity, which can be detachably sealed by a plug. The plug can reduce a pressure within the cavity or allow removal of gas bubbles in the fluid held in the cavity.

Abstract: This application discloses a device that emits heat during operation, and an enclosure having walls forming a cavity to hold a first fluid. The walls also form a recess to retain a second fluid external from the cavity. The device can be disposed in the recess and at least partially submerged in the second fluid. The second fluid can absorb the heat emitted by the device and transfer the absorbed heat to the first fluid through the walls of the enclosure shared between the cavity and the recess. The enclosure can include an inlet port configured to allow the first fluid into the cavity and an outlet port configured to output the first fluid from the cavity. A flow of the first fluid through the cavity from the inlet port to the outlet port can dissipate the heat transferred from the device to the first fluid.

Abstract: This application discloses an device disposed on a substrate, and a heat sink disposed on the substrate over the device. The heat sink disposed on the substrate forms a cavity to hold a fluid between the heat sink and the device. The fluid can absorb heat emitted by the device and transfer at least a portion of the absorbed heat to the heat sink. A gasket can be disposed between and in contact with the substrate and the heat sink. The gasket can prevent the fluid from exiting the cavity formed by the heat sink disposed on the substrate. The heat sink can have an opening to the cavity, which can be detachably sealed by a plug. The plug can reduce a pressure within the cavity or allow removal of gas bubbles in the fluid held in the cavity.

Abstract: This application discloses a computing system to identify a stage of a logic pipeline described in a circuit design that, when implemented in configurable hardware, spans between partitions in the configurable hardware. The computing system can modify the circuit design to alter a timing for logic operations in the logic pipeline, which reduces slack in at least one stage in the logic pipeline adjacent to the identified stage in the logic pipeline. The computing system can utilize the slack reduced from at least one of the stages adjacent to the identified stage to increase a clock frequency in the configurable hardware or increase a time available for propagation delay associated with the identified stage. The computing system can generate a configuration for the configurable hardware that implements the logic pipeline with the altered timing in the configurable hardware.

Abstract: In a computing system having a data source, a memory, and a central processing unit (CPU), data is transferred from the data source to the memory by first monitoring signals from the CPU to determine whether data transfer is desired. If data transfer is desired, an optimized instruction set is generated which is specifically designed to cause the CPU to carry out the data transfer in an optimal manner. This optimized instruction set is sent to the CPU and is executed thereby to transfer the data quickly and efficiently. An apparatus for carrying out the above method comprises a determiner, an instruction generator, and a coupling circuit. The determiner monitors address and control signals from the CPU to determine whether data transfer is desired. In response to a determination that data transfer is desired, the determiner generates a run control signal.