Abstract: In one embodiment, a first dielectric film (24), and a second dielectric film (32) are formed over a substrate (10). The substrate is cured to at least partially change a property of the second dielectric film thereby forming an intermediate etch stop (46). A third dielectric film (42) is formed over the substrate (10). The substrate (10) is then etched to remove portions of the first dielectric film (24) and portions of the third dielectric film (42) using the intermediate etch stop (46) to form a portion of an interconnect opening (103). In an alternative embodiment, a resist layer (92), and portions of an interlevel dielectric layer (50) are etched. Upon completion of the step of etching, the photoresist layer (92) and portions of the interlevel dielectric layer (50) are completely removed.

Abstract: In accordance with embodiments of the present invention a trench-level dielectric film (26) and a via-level dielectric film (24) are formed overlying a semiconductor device substrate (10). A via opening (42) is etched in the trench-level dielectric film with a first etch chemistry that has a higher etch selectivity to the trench-level dielectric film (26) than to the via-level dielectric film (24). A trench opening (54) is patterned in a photoresist layer (52) overlying the trench-level dielectric film (26). The via-level dielectric film (24) is etched with a second etch chemistry to extend the via opening (42) into the via-level dielectric film (24). The trench-level dielectric film (26) is etched to form a trench opening.

Abstract: In one embodiment, a first dielectric film (24), and a second dielectric film (32) are formed over a substrate (10). The substrate is cured to at least partially change a property of the second dielectric film thereby forming an intermediate etch stop (46). A third dielectric film (42) is formed over the substrate (10). The substrate (10) is then etched to remove portions of the first dielectric film (24) and portions of the third dielectric film (42) using the intermediate etch stop (46) to form a portion of an interconnect opening (103). In an alternative embodiment, a resist layer (92), and portions of an interlevel dielectric layer (50) are etched. Upon completion of the step of etching, the photoresist layer (92) and portions of the interlevel dielectric layer (50) are completely removed.

Abstract: In accordance with embodiments of the present invention a trench-level dielectric film (26) and a via-level dielectric film (24) are formed overlying a semiconductor device substrate (10). A via opening (42) is etched in the trench-level dielectric film with a first etch chemistry that has a higher etch selectivity to the trench-level dielectric film (26) than to the via-level dielectric film (24). A trench opening (54) is patterned in a photoresist layer (52) overlying the trench-level dielectric film (26). The via-level dielectric film (24) is etched with a second etch chemistry to extend the via opening (42) into the via-level dielectric film (24). The trench-level dielectric film (26) is etched to form a trench opening.

Abstract: An interconnect structure having a dielectric layer with low dielectric constant is formed within an integrated circuit. In one embodiment of the invention, portions of a silicon dioxide layer (18) lying adjacent to a conductive interconnect (21) are removed to expose portions of a silicon nitride etch stop layer (16). A dielectric layer (22) having a low dielectric constant is then formed overlying the conductive interconnect (21) and the exposed portions of the silicon nitride etch stop layer (16). A portion of the dielectric layer (22) is then removed to expose the top surface of the conductive interconnect (21) to leave portions of the dielectric layer (22) between adjacent conductive interconnects (21). The resulting interconnect structure has reduced cross-talk between conductive interconnects (21) while avoiding prior art disadvantages of reduced thermal dissipation and increased mechanical stress.