Abstract: Apparatus might include a first plurality of signal lines, a second plurality of signal lines, a controller, a first die, and a second die. The controller, the first die, and the second die might each be connected to the first plurality of signal lines and connected to the second plurality of signal lines. The first die and the second die might each include termination circuitry connected to a particular signal line of the second plurality of signal lines. The first die might be configured to activate its termination circuitry in response to receiving a particular combination of signal values on the first plurality of signal lines. The second die might be configured to deactivate its termination circuitry in response to receiving the particular combination of signal values on the first plurality of signal lines.

Abstract: Memory devices might include an input/output (I/O) node, a termination device, an array of memory cells in communication with the I/O node through the termination device, and control circuitry, wherein the control circuitry is configured to compare an address received by the memory device to a plurality of instances of address information stored in the memory device. Each instance of address information of the plurality of instances of address information might correspond to a respective termination value stored in the memory device. In response to the memory device receiving an address matching an instance of address information stored in the memory device, the control circuitry might further be configured to activate the termination device using the respective termination value corresponding to the instance of address information matching the received address.

Abstract: Memory devices including a controller for access of an array of memory cells that is configured to accept a sequence of commands to cause the memory device to read a first set of data from the array of memory cells into a first register, load the first set of data into a first portion of a second register, write a set of test data to a second portion of the second register during a reading of a second set of data from the array of memory cells to the first register, read the set of test data from the second portion of the second register during the reading of the second set of data, and output the set of test data from the memory device during the reading of the second set of data.

Abstract: Memory devices might include an input/output (I/O) node, a termination device, an array of memory cells in communication with the I/O node through the termination device, and control circuitry, wherein the control circuitry is configured to compare an address received by the memory device to a plurality of instances of address information stored in the memory device. Each instance of address information of the plurality of instances of address information might correspond to a respective termination value stored in the memory device. In response to the memory device receiving an address matching an instance of address information stored in the memory device, the control circuitry might further be configured to activate the termination device using the respective termination value corresponding to the instance of address information matching the received address.

Abstract: Memories include a controller that, in response to receiving a command to perform an access operation on an array of memory cells, might be configured to perform the access operation on the array of memory cells using trims corresponding to trim settings for the access operation. The controller, in response to receiving a command or a command sequence while performing the access operation that is indicative of a desire to suspend the access operation and load updated trim settings, might be further configured to suspend the access operation, load updated trim settings for the access operation into a particular trim register of a plurality of trim registers, set updated trims for the access operation in response to the updated trim settings in the particular trim register, and resume the access operation using the updated trims.

Abstract: Methods of operating a memory system comprising a plurality of memory devices include loading respective sets of termination information to a subset of memory devices of the plurality of memory devices, and, for each memory device of the subset of memory devices, storing its respective set of termination information to an array of non-volatile memory cells of that memory device. For each memory device of the subset of memory devices, its respective set of termination information comprises address information of the memory system and one or more termination values associated with that address information.

Abstract: Memory devices including a controller for access of an array of memory cells that is configured to accept a sequence of commands to cause the memory device to read a first set of data from the array of memory cells into a first register, load the first set of data into a first portion of a second register, write a set of test data to a second portion of the second register during a reading of a second set of data from the array of memory cells to the first register, read the set of test data from the second portion of the second register during the reading of the second set of data, and output the set of test data from the memory device during the reading of the second set of data.

Abstract: Methods for verifying data path integrity are provided. One such method includes reading a partially programmed first set of data from an array of memory cells of the memory device into a page register of the memory device, loading the partially programmed first set of data into a cache register of the memory device, writing a partial set of test data to a portion of the cache register not containing the partially programmed first set of data during a read of a second set of data from the array of memory cells to the page register, reading the partial set of test data from the cache register during the read of the second set of data from the array of memory cells to the page register, and comparing the partial set of test data read from the cache register to the original partial set of test data.

Abstract: Memories include a controller that, in response to receiving a command to perform an access operation on an array of memory cells, might be configured to perform the access operation on the array of memory cells using trims corresponding to trim settings for the access operation. The controller, in response to receiving a command or a command sequence while performing the access operation that is indicative of a desire to suspend the access operation and load updated trim settings, might be further configured to suspend the access operation, load updated trim settings for the access operation into a particular trim register of a plurality of trim registers, set updated trims for the access operation in response to the updated trim settings in the particular trim register, and resume the access operation using the updated trims.

Abstract: Apparatus include an external controller, a memory storing trim settings corresponding to a plurality of modes of operation, and a memory device. The memory device includes an array of memory cells, an internal controller, and a trim register array. The internal controller is configured to load trim settings to a trim register of the trim register array in response to a command received from the external controller, to set trims in response to the trim settings in response to receiving an access command associated with the trim settings, and to perform an access operation on the array of memory cells using the trims in response to receiving the access command. The external controller is configured, in response to receiving a command indicative of a desired mode of operation, to select trim settings corresponding to the desired mode of operation, and to transmit the selected trim settings to the memory device.

Abstract: Methods of operating a memory system comprising a plurality of memory devices include loading respective sets of termination information to a subset of memory devices of the plurality of memory devices, and, for each memory device of the subset of memory devices, storing its respective set of termination information to an array of non-volatile memory cells of that memory device. For each memory device of the subset of memory devices, its respective set of termination information comprises address information of the memory system and one or more termination values associated with that address information.

Abstract: Methods for termination of signal lines within a memory system include appointing a particular memory device of a plurality of memory devices to act as a termination device during a memory device operation on a memory device of the plurality of memory devices corresponding to a particular address of the memory system, wherein appointing the particular memory device to act as a termination device comprises storing termination information in the particular memory device corresponding to the particular address.

Abstract: Methods include configuring termination devices of a driver circuit of a memory device, storing a first plurality of trim values representative of the configuration of the termination devices of the driver circuit, transferring a second plurality of trim values to a different memory device, and configuring a plurality of termination devices of a driver circuit of the different memory device in response to the second plurality of trim values. Methods further include determining configuration information corresponding to a configuration of a particular driver circuit of a memory device adjusted to a desired impedance, storing a first set of trim values representative of the configuration information, and adjusting an impedance of a different driver circuit of the memory device in response to the first set of trim values and a correction factor representative of expected differences in characteristics between the particular driver circuit and the different driver circuit.

Abstract: Methods for verifying data path integrity are provided. One such method includes reading a partially programmed first set of data from an array of memory cells of the memory device into a page register of the memory device, loading the partially programmed first set of data into a cache register of the memory device, writing a partial set of test data to a portion of the cache register not containing the partially programmed first set of data during a read of a second set of data from the array of memory cells to the page register, reading the partial set of test data from the cache register during the read of the second set of data from the array of memory cells to the page register, and comparing the partial set of test data read from the cache register to the original partial set of test data.

Abstract: Apparatus include an external controller, a memory storing trim settings corresponding to a plurality of modes of operation, and a memory device. The memory device includes an array of memory cells, an internal controller, and a trim register array. The internal controller is configured to load trim settings to a trim register of the trim register array in response to a command received from the external controller, to set trims in response to the trim settings in response to receiving an access command associated with the trim settings, and to perform an access operation on the array of memory cells using the trims in response to receiving the access command. The external controller is configured, in response to receiving a command indicative of a desired mode of operation, to select trim settings corresponding to the desired mode of operation, and to transmit the selected trim settings to the memory device.

Abstract: Apparatus include an array of memory cells, a controller to perform access operations on the array of memory cells, a clock signal node, a counter having an input selectively connected to the clock signal node, and a clock generator having an output connected to the input of the counter.

Abstract: Methods and memories for verifying data path integrity are provided. In one such method, a first set of data are read from a first register of a memory device while a second set of data are written to an array of the memory device. The read first set of data and the data written to the first register are compared to verify data path integrity.

Abstract: Methods including performing an access operation on a memory device using trims corresponding to trim settings, receiving a command to suspend the access operation, loading updated trim settings into a particular trim register of the memory device, setting updated trims for the access operation in response to the updated trim settings of the particular trim register, and resuming the access operation using the updated trims. Apparatus including an external controller and a memory device having an internal controller configured to set trims in response to trim settings and to perform an access operation on an array of memory cells using the trims in response to receiving the access command, wherein the external controller is configured to select trim settings corresponding to a desired mode of operation, and to transmit the selected trim settings to the memory device.

Abstract: Methods include configuring termination devices of a driver circuit of a memory device, storing a first plurality of trim values representative of the configuration of the termination devices of the driver circuit, transferring a second plurality of trim values to a different memory device, and configuring a plurality of termination devices of a driver circuit of the different memory device in response to the second plurality of trim values. Methods further include determining configuration information corresponding to a configuration of a particular driver circuit of a memory device adjusted to a desired impedance, storing a first set of trim values representative of the configuration information, and adjusting an impedance of a different driver circuit of the memory device in response to the first set of trim values and a correction factor representative of expected differences in characteristics between the particular driver circuit and the different driver circuit.

Abstract: Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory to address individual memory units in the NAND memory can be identified. The defined number of address cycles in which to operate can be selected in order to address the individual memory units in the NAND memory. Either the memory controller or the NAND memory can be configured to operate at the selected number of address cycles where the individual memory units in the NAND memory are uniquely addressable using a multi die select (MDS).