Abstract: A method of addressing units of data stored in a memory using logical addresses. The logical addresses include fewer bits than necessary to uniquely address each unit of data stored in the memory. Translation of a logical address begins with analysis of a first logical address associated with a first unit of data to determine whether it is an even logical address or an odd logical address. A number of similar steps are taken in either case. If the first logical address is an even logical address these steps include coupling the first number of bits to an even translation table. The even translation table stores an even pointer for each even logical address. Each even pointer includes fewer bits than necessary to uniquely identify each unit of data stored in the memory. The even translation table couples the pointer to a first memory, which stores units of data associated with even logical addresses. Finally, in response to the even pointer a first unit of data is output from the even memory.

Abstract: A port expander for providing an external memory to be used with a microcontroller but recapturing the use of I/O ports which are lost due to the coupling of the memory. Two ports are coupled to the microcontroller for transfer of address and data information. An EPROM in the port expander provides the external memory while a special function register is used to couple data to and from two I/O ports. A configuration register provides programmability of which address values address the memory and which address values address the special function registers.

Abstract: A read-only memory incorporated on a single substrate for use with a microprocessor system is described. The memory includes a transceiver for passing data and first address signals, and the transceiver has a first side for coupling to a first plurality of lines. A first latch for latching the first address signals is provided, wherein the first latch has a first side coupled to a second side of the transceiver. A first buffer is provided, the first buffer having a first side coupled to a second side of the first latch. A second buffer for buffering second address signals is provided, the second buffer having a first side for coupling to a second plurality of lines. A second latch for latching the second address signals is provided, wherein the second latch has a first side coupled to a second side of the second buffer. A third buffer is provided, and the third buffer has a first side coupled to a second side of the second latch. A memory array for storing the data is further provided.