Abstract: A computer micro-architecture employing a prevalidated cache tag design includes circuitry to support virtual address aliasing and multiple page sizes. Support for various levels of address aliasing are provided through a physical address CAM, page size mask compares and a column copy tag function. Also supported are address aliasing that invalidates aliased lines, address aliasing with TLB entries with the same page sizes, and address aliasing the TLB entries of different sizes. Multiple page sizes are supported with extensions to the prevalidated cache tag design by adding page size mask RAMs and virtual and physical address RAMs.

Abstract: In a computer architecture using a prevalidated tag cache design, logic circuits are added to enable store and invalidation operations without impacting integer load data access times and to invalidate stale cache lines. The logic circuits may include a translation lookaside buffer (TLB) architecture to handle store operations in parallel with a smaller, faster integer load TLB architecture. A store valid module is added to the TLB architecture. The store valid module sets a valid bit when a new cache line is written. The valid bit is cleared on the occurrence of an invalidation operation. The valid bit prevents multiple store updates or invalidates for cache lines that are already invalid. In addition, an invalidation will block load hits on the cache line. A control logic is added to remove stale cache lines. When a cache line fill is being processed, the control logic determines if the cache line exists in any other cache segments.

Abstract: A system and method are disclosed which determine in parallel for multiple levels of a multi-level cache whether any one of such multiple levels is capable of satisfying a memory access request. Tags for multiple levels of a multi-level cache are accessed in parallel to determine whether the address for a memory access request is contained within any of the multiple levels. For instance, in a preferred embodiment, the tags for the first level of cache and the tags for the second level of cache are accessed in parallel. Also, additional levels of cache tags up to N levels may be accessed in parallel with the first-level cache tags. Thus, by the end of the access of the first-level cache tags it is known whether a memory access request can be satisfied by the first-level, second-level, or any additional N-levels of cache that are accessed in parallel.

Abstract: A scroll compressor is provided with structure that allows a reduction or modulation in mass flow capacity. Structure is provided for controlling the back pressure force tending to bias one scroll into other. This structure defines two distinct back pressure chambers. Pressure fluid is not supplied to at least one of the back pressure chambers during modulated operation.

Abstract: A scroll compressor having a housing containing an orbiting scroll and a non-orbiting scroll each having a base formed with a free side and a compression side and having an involute extending generally normally from the compression side, each the involute terminating in an axially outer, substantially planar edge and having a radially outer inlet end and a radially inner discharge end, the scrolls being mounted within the housing in mating arrangement about a center axis of the involutes for relative orbital motion for compressing gas between the base and adjacent side portions of the involutes, the orbiting scroll having special bearing structure for eliminating the laterally directed tipping forces which are generally experienced by the orbiting scrolls of conventional scroll compressors, the bearing structure having a bearing hub integral with the discharge end of the involute of the orbiting scroll, the hub having a cylindrical bore oriented substantially normal to the compression side of the orbiting scr

Abstract: A safety bumper pad includes a bumper pad, a mattress retaining sheet, and a plurality of positive locking straps. A bumper cover is sewn around a bumper cushion to form the bumper pad. The mattress retaining sheet is sewn on the bottom of the bumper pad such that a mattress may be inserted therein. The mattress retaining sheet is deep enough to allow the entire bumper pad to protrude above the mattress. A plurality of positive locking straps are attached to substantially the top of the bumper pad. The positive locking straps include a strap portion, a female locking member, and a male locking portion. The female locking member is attached to one end of the strap portion. The male locking member contains a loop section through which the other end of the strap portion is inserted. The male and female locking members are pulled around at least one crib rail and then the male locking member is inserted into the female locking member.

Abstract: A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers.

Abstract: A device for electrically connects a plurality of electrical devices with a source of electrical energy. The device includes a base, a primary power cord, a primary reel, the capability of receiving a plurality of separate conductors, and at least two secondary reels. The primary power cord is adapted for connection with the source of electrical energy. The primary reel is attached to the base and has the primary power cord at least partially wound thereon. The primary reel is biased in a first direction and rotatable in the opposite direction which permits extension and retraction of the primary power cord. Each of the plurality of separate conductors is adapted for electrical connection with the primary power cord and adapted for providing a remote source of electrical energy to the electrical device. Each of the secondary reels include one of the conductors at least partially wound thereon for effecting extension and retraction thereof.

Abstract: A scroll compressor having a housing containing a non-orbiting scroll and an orbiting scroll and a crankshaft having an eccentric mounted on the orbiting scroll, the non-orbiting scroll being fixed in operative position on the housing by a plurality of pairs of cooperating, mating key and keyway type components provided on the housing and non-orbiting scroll and mating with predesigned pressure contact, wherein all of the pairs have been mated with substantially equal pressure contact prior to fixing the positions of the pairs on the housing, and wherein the mated pairs allow axial compliance motion of the non-orbiting scroll while providing predetermined resistance to the motion.

Abstract: A data cache memory apparatus permits load and store instructions to be issued out-of-order. The apparatus includes a memory. An instruction issue apparatus issues an instruction stream containing store and load instructions. The store instructions are completed in two passes, namely a store allocate pass and a corresponding store commit pass. A cache control is connected to the instruction issue apparatus and the memory and issues store and load addresses to the memory in response to instructions from the instruction issue apparatus. A store history table is connected to the cache control and stores a record of the addresses of the memory where data are to be stored, and thus a record of the store allocate passes issued by the instruction issue apparatus for which no corresponding store commit pass has been completed. The cache control responds to the subsequent corresponding store commit pass to issue the store address to the memory and to clear the store instruction from the store history table.

Abstract: A clock multiplier is selectable to provide either an unmultiplied input clock to the internal clock line or a multiplied clock signal, depending upon the state of a test mode input signal. By providing the circuitry on a integrated circuit chip, the chip can be driven at its normal operating frequency using lower-frequency test equipment. One multiplier device includes a plurality of series-connected one-shots.

Abstract: A scan diagnostics apparatus and method is useful in connection with the memory integrated circuit. A shift register is provided which can receive data in parallel from the input register and output the data serially. The shift register can receive serial data and output in parallel either to the input buffer or the output buffer. Preferably the shift register can receive in parallel, data from the output buffer and output the data serially.

Abstract: A circuit means for detecting data errors in VLSI processing circuits at the earliest point such an error occurs in the processing stream or (in different modes) at any selected point therein, and for providing the prior operands and faulty (intermediate) output data together with an indication of what is wrong with the data. Described are registers and/or means for controlling the mode of the circuitry, error detection means (being, for example, parity check circuits), and an output means for providing the output in an organized way responsive to the controlling means and the output of the error detecton means. The method of using such a circuit is inherent in the disclosure.