Abstract: An apparatus and method in a computer system allows a software application to specify an intended stride access when writing data elements into a memory. A memory control in the computer system writes data in a manner that provides improved access performance when accesses to the data elements are performed using the intended stride. The memory system uses a hashing mechanism that uses the intended stride to store the data elements in such a way that accessing the data elements at the intended stride will ensure that consecutive accesses are not to the same group or bank of memory. Sequential accesses of the data elements also are ensured not to be directed to the same group or bank of memory. The memory can be divided into memory portions; different memory portions of the computer storage can have different intended strides.

Abstract: In a data communication system for communicating data between a plurality of data communicating entities, data is transmitted simultaneously from at least a first data communicating entity and a second data communicating entity onto a serial data ring. A first portion of the serial data ring is cross coupled to a second portion of the serial data ring so that data from the first data communicating entity avoids conflict with data from the second data communicating entity, thereby emulating a forward and reverse transmission on a single unidirectional serial ring.

Abstract: In a data communication system for communicating data between a plurality of data communicating entities, data is transmitted simultaneously from at least a first data communicating entity and a second data communicating entity onto a serial data ring. A first portion of the serial data ring is cross coupled to a second portion of the serial data ring so that data from the first data communicating entity avoids conflict with data from the second data communicating entity, thereby emulating a forward and reverse transmission on a single unidirectional serial ring.

Abstract: A cooling plate assembly for transferring heat from electronic components mounted on a circuit board includes both fixed and articulated interfaces. A fixed-gap coldplate is positioned over and in thermal contact with (e.g., through an elastomerically compressive pad thermal interface material) electronic components mounted on the circuit board's top surface. An articulated coldplate is positioned over and in thermal contact with at least one electronic component mounted on the circuit board's top surface. In the preferred embodiments, the articulated coldplate is spring-loaded against one or more high power processor components having power dissipation greater than that of the electronic components under the fixed-gap cooling plate. Thermal dissipation channels in the coldplates are interconnected by flexible tubing, such as copper tubing with a free-expansion loop.

Abstract: In a computer architecture using a prevalidated tag cache design, logic circuits are added to enable store and invalidation operations without impacting integer load data access times and to invalidate stale cache lines. The logic circuits include a translation lookaside buffer (TLB) architecture to handle store operations in parallel with a smaller, faster integer load TLB architecture. A store valid module, added to the TLB architecture, sets a valid bit when a new cache line is written. The valid bit is cleared on the occurrence of an invalidation operation. The valid bit prevents multiple store updates or invalidates for cache lines that are already invalid.

Abstract: A method, and a corresponding apparatus, mask error detection and correction latency during multilevel cache transfers. The method includes the steps of transferring error protection encoded data lines from a first cache, checking the error protection encoded data lines for errors, wherein the checking is completed after the transferring begins, receiving the error protection encoded data lines in a second cache, and upon detecting an error in a data line, preventing further transfer of the data line from the second cache.

Abstract: In a computer system, a parallel, distributed function lookaside buffer (TLB) includes a small, fast TLB and a second larger, but slower TLB. The two TLBs operate in parallel, with the small TLB receiving integer load data and the large TLB receiving other virtual address information. By distributing functions, such as load and store instructions, and integer and floating point instructions, between the two TLBs, the small TLB can operate with a low latency and avoid thrashing and similar problems while the larger TLB provides high bandwidth for memory intensive operations. This mechanism also provides a parallel store update and invalidation mechanism which is particularly useful for prevalidated cache tag designs.

Abstract: In a computer architecture using a prevalidated tag cache design, logic circuits are added to enable store and invalidation operations without impacting integer load data access times and to invalidate stale cache lines. The logic circuits may include a translation lookaside buffer (TLB) architecture to handle store operations in parallel with a smaller, faster integer load TLB architecture. A store valid module is added to the TLB architecture. The store valid module sets a valid bit when a new cache line is written. The valid bit is cleared on the occurrence of an invalidation operation. The valid bit prevents multiple store updates or invalidates for cache lines that are already invalid. In addition, an invalidation will block load hits on the cache line. A control logic is added to remove stale cache lines. When a cache line fill is being processed, the control logic determines if the cache line exists in any other cache segments.

Abstract: In a computer architecture using a prevalidated tag cache design, logic circuits are added to enable store and invalidation operations without impacting integer load data access times and to invalidate stale cache lines. The logic circuits may include a translation lookaside buffer (TLB) architecture to handle store operations in parallel with a smaller, faster integer load TLB architecture. A store valid module is added to the TLB architecture. The store valid module sets a valid bit when a new cache line is written. The valid bit is cleared on the occurrence of an invalidation operation. The valid bit prevents multiple store updates or invalidates for cache lines that are already invalid. In addition, an invalidation will block load hits on the cache line.

Abstract: A source cache transfers data to an intermediate cache along a data connection. The intermediate cache is provided between the source cache and a target, and includes a memory array. The source cache may also transfer data to the target along the data connection while bypassing the memory array of the intermediate cache.

Abstract: A method for modeling the performance of a test processor using a processor simulator program. The processor simulator program is configured for executing an application program against an input dataset. The method includes obtaining a plurality of representative samples, each of the plurality of representative samples representing a respective group of initial samples having substantially similar runtime performance characteristics. Each of the plurality of representative samples has a plurality of dynamic instructions, wherein dynamic instructions from the plurality of representative samples represents only a subset of a stream of dynamic instructions generated when the application program is executed against the input dataset. The stream of dynamic instructions is segmentable into a plurality of initial samples of which the respective group of initial samples is a subset. The method further includes obtaining a set of performance indicators from the processor simulator program.

Abstract: A method and apparatus consolidate ports on a unified cache. The apparatus uses plurality of access connections with a single port of a memory. The apparatus comprises multiplexor and a logic circuit. The multiplexor is connected to the plurality of access connections. The multiplexor has a control input and a memory connection. The logic circuit produces an output signal tied to the control input. In another form, the apparatus comprises means for selectively coupling a single one of the plurality of access connections to the memory, and a means for controlling the means for coupling. Preferably, the plurality of access connections comprise a data connection and an instruction connection, and the memory is cache memory. The method uses a single memory access connection for a plurality of access types. The method accepts one or more memory access requests on one or more respective ones of a plurality of connections.

Abstract: In a computer system, a parallel, distributed function lookaside buffer (TLB) includes a small, fast TLB and a second larger, but slower TLB. The two TLBs operate in parallel, with the small TLB receiving integer load data and the large TLB receiving other virtual address information. By distributing functions, such as load and store instructions, and integer and floating point instructions, between the two TLBs, the small TLB can operate with a low latency and avoid thrashing and similar problems while the larger TLB provides high bandwidth for memory intensive operations. This mechanism also provides a parallel store update and invalidation mechanism which is particularly useful for prevalidated cache tag designs.

Abstract: A method, and a corresponding apparatus, mask error detection and correction latency during multilevel cache transfers. The method includes the steps of transferring error protection encoded data lines from a first cache, checking the error protection encoded data lines for errors, wherein the checking is completed after the transferring begins, receiving the error protection encoded data lines in a second cache, and upon detecting an error in a data line, preventing further transfer of the data line from the second cache.

Abstract: In a computer system, a parallel, distributed function lookaside buffer (TLB) includes a small, fast TLB and a second larger, but slower TLB. The two TLBs operate in parallel, with the small TLB receiving integer load data and the large TLB receiving other virtual address information. By distributing functions, such as load and store instructions, and integer and floating point instructions, between the two TLBs, the small TLB can operate with a low latency and avoid thrashing and similar problems while the larger TLB provides high bandwidth for memory intensive operations. This mechanism also provides a parallel store update and invalidation mechanism which is particularly useful for prevalidated cache tag designs.

Abstract: Methods and apparatus mask the latency of error detection and/or error correction applied to data transferred between a first memory and a second memory. The method comprises determining whether there is an error in a data unit in the first memory; transferring data based on the data unit from the first memory to a second memory, wherein the transferring step commences before completion of the determining step; and disabling at least part of the second memory if the determining step detects an error in the data unit. The disabling step may be accomplished, for example, by disabling the buffering of an address of the data unit or stalling the second memory.

Abstract: The inventive cache uses a queuing structure which provides out-of-order cache memory access support for multiple accesses, as well as support for managing bank conflicts and address conflicts. The inventive cache can support four data accesses that are hits per clocks, support one access that misses the L1 cache every clock, and support one instruction access every clock. The responses are interspersed in the pipeline, so that conflicts in the queue are minimized. Non-conflicting accesses are not inhibited, however, conflicting accesses are held up until the conflict clears. The inventive cache provides out-of-order support after the retirement stage of a pipeline.

Abstract: In a computer architecture using a prevalidated tag cache design, logic circuits are added to enable store and invalidation operations without impacting integer load data access times and to invalidate stale cache lines. The logic circuits may include a translation lookaside buffer (TLB) architecture to handle store operations in parallel with a smaller, faster integer load TLB architecture. A store valid module is added to the TLB architecture. The store valid module sets a valid bit when a new cache line is written. The valid bit is cleared on the occurrence of an invalidation operation. The valid bit prevents multiple store updates or invalidates for cache lines that are already invalid. In addition, an invalidation will block load hits on the cache line. A control logic is added to remove stale cache lines. When a cache line fill is being processed, the control logic determines if the cache line exists in any other cache segments.

Abstract: The inventive cache processes multiple access requests simultaneously by using separate queuing structures for data and instructions. The inventive cache uses ordering mechanisms that guarantee program order when there are address conflicts and architectural ordering requirements. The queuing structures are snoopable by other processors of a multiprocessor system. The inventive cache has a tag access bypass around the queuing structures, to allow for speculative checking by other levels of cache and for lower latency if the queues are empty. The inventive cache allows for at least four accesses to be processed simultaneously. The results of the access can be sent to multiple consumers. The multiported nature of the inventive cache allows for a very high bandwidth to be processed through this cache with a low latency.

Abstract: A CAM providing for the identification of a plurality of multiple bit tag values stored in the CAM, having logic circuitry for comparing each bit of an inputted test value to the corresponding bits of all stored tag values. A bit select is employed for generating a plurality of test bits for sequential input into the logic circuitry. The logic circuitry compares the plurality of test bits to the corresponding bit of each stored tag value and generates a “hit” signal if the selected bit is the same as the corresponding bit of the stored tag value. Storage means are employed for recording the results of the compare with the M hit signal.