Patents by Inventor Terry Lines

Terry Lines has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for eliminating a mask layer during thin film resistor manufacturing
    Patent number: 7829428
    Abstract: A method is disclosed for eliminating a mask layer during the manufacture of thin film resistor circuits. The method of the present invention enables the simultaneous etching of both deep vias and shallow vias using one mask layer instead of two mask layers. A high selectivity film layer of silicon nitride is formed on the ends of a thin film resistor layer. The thickness of the silicon nitride causes the etch time for a shallow via to the thin film resistor to be approximately equal to an etch time for a deep via that is etched through dielectric material to an underlying patterned metal layer.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: November 9, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Yaojian Leng, Rodney Hill, Terry Lines
  • System and method for selectively modifying a wet etch rate in a large area
    Patent number: 7172973
    Abstract: A system and method is disclosed for selectively increasing a wet etch rate of a large raised area portion of a semiconductor wafer with respect to a wet etch rate of a small raised area portion of the semiconductor wafer. A resist mask on the semiconductor wafer is etched to create a large via over the large raised area portion and a small via over the small raised area portion. An ion implantation beam is applied with an impact direction that enables ions to pass through the large via but does not enable ions to pass through the small via. The ions that pass through the large via increase the wet etch rate of the underlying portion of the semiconductor wafer. In one embodiment the impact direction has a tilt angle of forty five degrees and a rotation angle of forty five degrees.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: February 6, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Richard W. Foote, William M. Coppock, Victor M. Torres, Terry Lines
  • Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor
    Patent number: 7161216
    Abstract: A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the cost and complexity associated with the fabrication of a semiconductor circuit that includes a depletion-mode transistor.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: January 9, 2007
    Assignee: National Semiconductor Corporation
    Inventor: Terry Lines
  • Method for forming a depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor
    Patent number: 7144795
    Abstract: A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the cost and complexity associated with the fabrication of a semiconductor circuit that includes a depletion-mode transistor.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: December 5, 2006
    Assignee: National Semiconductor Corporation
    Inventor: Terry Lines
  • Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor
    Patent number: 6703670
    Abstract: A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the cost and complexity associated with the fabrication of a semiconductor circuit that includes a depletion-mode transistor.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: March 9, 2004
    Assignee: National Semiconductor Corporation
    Inventor: Terry Lines