Abstract: An apparatus and method in a computer system allows a software application to specify an intended stride access when writing data elements into a memory. A memory control in the computer system writes data in a manner that provides improved access performance when accesses to the data elements are performed using the intended stride. The memory system uses a hashing mechanism that uses the intended stride to store the data elements in such a way that accessing the data elements at the intended stride will ensure that consecutive accesses are not to the same group or bank of memory. Sequential accesses of the data elements also are ensured not to be directed to the same group or bank of memory. The memory can be divided into memory portions; different memory portions of the computer storage can have different intended strides.

Abstract: Methods and apparatus that may be utilized to improve the scalability of multi-processor systems are provided. Data packets constructed in accordance with a defined coherence protocol may be encapsulated in standard I/O packets. As a result, the same interconnect fabric may be used to route coherent data traffic and I/O data traffic.

Abstract: A unified tag subsystem for a multilevel cache memory system. The unified tag subsystem receives a cache line address including a tag index portion, a high order part and an optional cache line extension field. The tag index portion indexes a tag memory which has way-specific address tags, and lower level flags. A comparator compares the high order part with each way-specific address tag to detect a match. Lower level hit logic determines a hit when comparator detects a match and the lower level flag indicates a valid lower level cache entry; and an upper level hit logic determines a higher level cache hit when the comparator detects a match and the upper level valid is set. In particular embodiments, lower level flag indicates a way of storage where associated data may be found in lower level cache data memory.

Abstract: A unified tag subsystem for a multilevel cache memory system. The unified tag subsystem receives a cache line address including a tag index portion, a high order part and an optional cache line extension field. The tag index portion indexes a tag memory which has way-specific address tags, and lower level flags. A comparator compares the high order part with each way-specific address tag to detect a match. Lower level hit logic determines a hit when comparator detects a match and the lower level flag indicates a valid lower level cache entry; and an upper level hit logic determines a higher level cache hit when the comparator detects a match and the upper level valid is set. In particular embodiments, lower level flag indicates a way of storage where associated data may be found in lower level cache data memory.