Abstract: High performance switching network topologies and frame addressing techniques therefor are disclosed. A two-dimensional Fibre Channel switch fabric is disclosed which combines a Class 1 connection space-division multiplexing sub-fabric, and Class 2 and 3 connectionless space- and time-division multiplexing sub-fabric. Networking topologies are disclosed for combining multiple modules to increase the number of supported ports. Addressing and frame routing techniques are provided for routing frames to any port in any module of a large interconnected network of modules.

Abstract: High performance switching network topologies and frame addressing techniques therefor are disclosed. A two-dimensional Fiber Channel switch fabric is disclosed which combines a Class 1 connection space-division multiplexing sub-fabric, and Class 2 and 3 connectionless space- and time-division multiplexing sub-fabric. Networking topologies are disclosed for combining multiple modules to increase the number of supported ports. Addressing and frame routing techniques are provided for routing frames to any port in any module of a large interconnected network of modules.

Abstract: A method and apparatus for a multi-channel space-division switching network capable of providing dedicated line connections from a large number of inlets to a large number of outlets for either analog or digital communication. A flexible and highly modular space-division switching network is constructed using a basic digital exchange circuit element. This element is a basic building block which can be inexpensively manufactured and wired together in large numbers to form space-division switching networks which can be expanded or contracted according to a user's requirements and volume of communications. The building block element is constructed using line receiver/driver buffers as an interface to adapt a wide variety of communications media to the internal electronic media of the space-division switching network. The element also includes bus driver/receivers which are used to transfer communication information to and from intrastage and interstage buses.

Abstract: An improvement in facility management systems that allows an electronic control unit to be interfaced with a pneumatic cylinder unit. The digital pneumatic modulator of the improvement includes a solenoid valve controlled pneumatic input port, a solenoid valve controlled pneumatic exhaust port, and a flow controlled pneumatic exit port for connection with a pneumatic cylinder.

Abstract: A data processing system including a central processing unit and external memory. The central processing unit has an arithmetic logic unit having first and second inputs and an output for outputting data. The arithmetic logic unit inputs are selectively connected to the outputs of a plurality of addressable registers which registers have inputs connectable to the arithmetic logic unit output for receiving and storing data therefrom. Additionally, the central processing unit has a read only memory capable of storing a plurality of addressable control instructions and having a plurality of outputs for supplying control signals in dependence upon the addressed control instructions and means capable of addressing control instructions stored in the read only memory in a predetermined sequence, or addressing a selected one of said word locations in dependence upon the data outputted from the arithmetic logic unit.

Abstract: A central processing unit (CPU) is disclosed which can be used in a microprocessor and which has a relatively simple architecture enabling it to perform rapid data processing operations. The CPU has a plurality of registers, an arithmetic logic unit (ALU), and a multiplexor which selects one of the ALU operands. A relatively large scratchpad is included in the CPU to eliminate time-consuming addressing of memories outside the CPU. A parallel architecture and the ability to perform simultaneous operations also enhance the CPU speed. The CPU control unit has a read only memory (ROM) for storage of micro control instructions and a program counter capable of addressing the ROM either sequentially or in accordance with a specific address for execution of jump instructions.