Patents by Inventor Terry Remple

Terry Remple has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12463644
    Abstract: Techniques and mechanisms for using multiple delay line circuits to detect a change to the frequency of a periodic signal. In an embodiment, a first delay line receives the periodic signal from a phase locked loop, and generates first bits which include an indication of a first edge segment of the delay line. Another two delay lines receive respective bits which are variously based on a sampling of the first bits. The other two delay lines each output a respective one of two bit sequences, which are sampled or otherwise used to determine the transitioning of a clock signal. In another embodiment, the frequency of the clock signal is determined based on one of a threshold minimum period of time that the frequency of the periodic signal is stable, a threshold minimum frequency of the periodic signal, or a threshold minimum increase to the frequency of the periodic signal.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: November 4, 2025
    Assignee: Intel Corporation
    Inventor: Terry Remple
  • Patent number: 12353235
    Abstract: Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: July 8, 2025
    Assignee: Intel Corporation
    Inventor: Terry Remple
  • Publication number: 20230396249
    Abstract: Techniques and mechanisms for using multiple delay line circuits to detect a change to the frequency of a periodic signal. In an embodiment, a first delay line receives the periodic signal from a phase locked loop, and generates first bits which include an indication of a first edge segment of the delay line. Another two delay lines receive respective bits which are variously based on a sampling of the first bits. The other two delay lines each output a respective one of two bit sequences, which are sampled or otherwise used to determine the transitioning of a clock signal. In another embodiment, the frequency of the clock signal is determined based on one of a threshold minimum period of time that the frequency of the periodic signal is stable, a threshold minimum frequency of the periodic signal, or a threshold minimum increase to the frequency of the periodic signal.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 7, 2023
    Applicant: Intel Corporation
    Inventor: Terry Remple
  • Publication number: 20220019258
    Abstract: Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.
    Type: Application
    Filed: October 1, 2021
    Publication date: January 20, 2022
    Inventor: Terry Remple