Patents by Inventor Terry Richard Heidmann

Terry Richard Heidmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stress relieving structure for semiconductor device
    Patent number: 10896887
    Abstract: A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a different elastic modulus than the metal layer or layer stack over a temperature range.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: January 19, 2021
    Assignee: Infineon Technologies AG
    Inventors: Marius Aurel Bodea, Terry Richard Heidmann, Marianne Mataln, Claudia Sgiarovello
  • Stress Relieving Structure for Semiconductor Device
    Publication number: 20190348382
    Abstract: A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a different elastic modulus than the metal layer or layer stack over a temperature range.
    Type: Application
    Filed: March 7, 2019
    Publication date: November 14, 2019
    Inventors: Marius Aurel Bodea, Terry Richard Heidmann, Marianne Mataln, Claudia Sgiarovello
  • Semiconductor Device with Stress Relieving Structure
    Publication number: 20190348373
    Abstract: A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a smaller elastic modulus than the metal layer or layer stack over a temperature range.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 14, 2019
    Inventors: Marius Aurel Bodea, Terry Richard Heidmann, Marianne Mataln, Claudia Sgiarovello