Abstract: An improved means and method is described for providing a conductive pillar in a via between multiple layers of conductors on planar electronic structures such as integrated circuits. A lower first conductor layer is formed on the device substrate and covered with an electrically conducting etch-stop layer and a second conductor layer. The second conductor layer is masked to define the conductive via and etched selectively and anisotropically until the etch-stop layer is reached. The exposed portions of the etch-stop layer are then removed. The remaining portions of the etch-stop layer and second conductor layer together form the conductive pillar. The lower first metal layer is patterned and then covered with a planarizing layer, such as a polyimide, having a thickness at least equal to the height of the pillar. The planarizing layer is uniformly etched to expose the top of the pillar and then an upper metal layer deposited over the remaining polyimide and in contact with the top of the pillar.

Abstract: A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a polycrystalline semiconductor region, above a doped channel-stop region which acts as a field guard. A single mask layer determines the location and spacing of the buried portions of the isolation walls, the channel-stops, and the buried layers.

Abstract: A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a non-single crystal semiconductor region, above a doped channel-stop region. A single mask layer determines the location and spacing of the non-single crystal portion of the isolation walls, the channel-stops, and the buried layers.

Abstract: A process is described for fabricating self-aligned buried doped regions in semiconductor devices and integrated circuits which avoids any need for delineation of the buried doped regions in the active portions of the device. Avoiding delineation improves the quality of the epitaxial layer used to cover the buried doped regions thereby improving overall performance and yield. Multiple mask layers are used in connection with a single mask pattern to achieve self-alignment. One mask layer consists of a material with a modifiable etch rate, e.g. polysilicon. A portion of the single crystal substrate is rendered non-single crystal and used as an alignment key which is propagated through the epitaxial layer grown over the undelineated buried doped regions. The dimensions and separations of the self-aligned buried doped regions can be precisely controlled.

Abstract: A structure is provided which affords radiation protection to semiconductor devices and which specifically prevents soft failures in semiconductor memories caused by alpha particle radiation. The protection is provided by a metallic radiation shield formed on but insulated from the semiconductor memory array. The radiation shield is formed on the semiconductor devices while they are still in wafer form but after the normal device fabrication has been completed.