Abstract: A look ahead column redundancy circuit provides high speed memory access to both regular memory arrays and redundant memory arrays. In the preferred embodiment of the present invention, the information on both the address bus and the information on the next address bus are decoded by redundant column decoders in parallel. The decoded information from the redundant column decoders is then provided to a redundancy column pathway as the addressing information from the address bus and the next address bus is provided to a main column pathway. The information on the address bus is latched when beginning at a new column address. The information on the next address bus is latched for the next column address when operating in a burst cycle mode. The main column pathway preferably includes a latch, a main column decoder and a main column select circuit.

Abstract: An apparatus for sharing redundancy circuits between memory arrays within a semiconductor memory device includes at least two main memory arrays comprised of a plurality of memory cells aligned in rows and/or columns and a shared redundancy circuit. The redundancy circuits preferably include a plurality of redundancy rows and a redundancy decoder which is configured for accessing the redundancy rows whenever a read or write operation involves use of a defective row within the main memory arrays for which a redundant row has been substituted. Preferably, each main memory array has access to the shared redundancy circuit. The shared redundancy circuit is used for substituting defective rows within a corresponding main memory array. The shared redundancy circuit provides extra redundant capacity to both of the main memory arrays.

Abstract: An equalization and precharge circuit precharges and equalizes local input/output (LIO) signal lines between each memory access operation within a memory circuit. The equalization and precharge circuit includes a local voltage circuit which maintains the level of the LIO signal lines at a standby voltage level during standby periods. Preferably, the standby voltage level is approximately equal to half of the supply voltage VCC. Separate precharge and equalization circuits are included to precharge and equalize the LIO signal lines between memory access operations. During precharge periods, a precharge control signal LIOPC is preferably at a logical high voltage level for a predetermined period of time between memory access operations, thereby forming a fixed-width pulse and raising the LIO signals to a known precharge level. The LIO signal lines are charged to a known level equal to the standby voltage level plus a voltage V(t) during the precharge and equalization period.

Abstract: The described embodiments of the present invention provide a circuit and method for a two level redundancy scheme for a semiconductor memory device. The memory device has one or more data blocks (12) with each data block (12) having an array of memory cells arranged in addressable rows and columns along row lines and column lines. Each array is configured into sub-blocks (14) with each sub-block having a plurality of the memory cells. The first level redundancy scheme includes a few redundant elements for each sub-block for the replacement of defective elements, as is common in many modern semiconductor devices. The second level redundancy scheme includes at least one redundant sub-block of memory cells as part of the main memory for a fully functional memory device or, as an extra level of redundancy for at least one sub-block of memory cells containing defects which are not repairable using the redundant elements.

Abstract: A look ahead column redundancy circuit provides high speed memory access to both regular memory arrays and redundant memory arrays. In the preferred embodiment of the present invention, the information on both the address bus and the information on the next address bus are decoded by redundant column decoders in parallel. The decoded information from the redundant column decoders is then provided to a redundancy column pathway as the addressing information from the address bus and the next address bus is provided to a main column pathway. The information on the address bus is latched when beginning at a new column address. The information on the next address bus is latched for the next column address when operating in a burst cycle mode. The main column pathway preferably includes a latch, a main column decoder and a main column select circuit.