Abstract: A set of runspaces with active connections are maintained in a pool. A set of timers are set and, based upon the timers, simple commands are submitted through the runspaces, to maintain the connections in an active state. The runspaces with the active connections can then be used from the cache, without having to open a new connection.

Abstract: A set of runspaces with active connections are maintained in a pool. A set of timers are set and, based upon the timers, simple commands are submitted through the runspaces, to maintain the connections in an active state. The runspaces with the active connections can then be used from the cache, without having to open a new connection.

Abstract: A carrier-free semiconductor package and a fabrication method thereof are provided. The fabrication method includes the steps of: providing a carrier having a plurality of electrical contacts formed thereon; mounting at least one chip on the carrier; electrically connecting the chip to the electrical contacts via a plurality of bonding wires; forming a coating layer on each of the electrical contacts to encapsulate a bonded end of each of the bonding wires on the electrical contacts; performing a molding process to form an encapsulant for encapsulating the chip, the bonding wires and the electrical contacts; and removing the carrier, such that bottom surfaces of the electrical contacts are exposed from the encapsulant. This obtains a semiconductor package not having a carrier, and the coating layers can enhance adhesion between the electrical contacts and the encapsulant.

Abstract: A lead-frame-based semiconductor package and a lead frame thereof are proposed. The semiconductor package includes: the lead frame having at least one die pad and a plurality of leads around the die pad, wherein a plurality of grooves and runners are formed on a surface of the die pad, and each of the grooves is connected to an edge of the die pad by at least one of the runners; at least one chip mounted on the other surface of the die pad and electrically connected to the plurality of leads; and an encapsulant for encapsulating the chip, with the runners and grooves being exposed from the encapsulant. Thus, the flash problem in the prior art can be solved by means of the runners and grooves.

Abstract: A carrier-free semiconductor package and a fabrication method thereof are provided. The fabrication method includes the steps of: providing a carrier having a plurality of electrical contacts formed thereon; mounting at least one chip on the carrier; electrically connecting the chip to the electrical contacts via a plurality of bonding wires; forming a coating layer on each of the electrical contacts to encapsulate a bonded end of each of the bonding wires on the electrical contacts; performing a molding process to form an encapsulant for encapsulating the chip, the bonding wires and the electrical contacts; and removing the carrier, such that bottom surfaces of the electrical contacts are exposed from the encapsulant. This obtains a semiconductor package not having a carrier, and the coating layers can enhance adhesion between the electrical contacts and the encapsulant.

Abstract: A leadframe-based non-leaded semiconductor package and method of fabricating the same is proposed, which is used for the fabrication of a non-leaded type of semiconductor package, such as QFN (Quad Flat No-lead) package. The proposed semiconductor packaging technology is characterized by the provision of a recessed portion in the paddle portion of the leadframe to help secure the encapsulation body more firmly in position without delamination, as well as help lower the position of the packaged chip to help prevent the bonding wires from being exposed to the outside of the encapsulation body. These features can help the finished package to be more reliable with increased good yield.

Abstract: A synchronous dynamic random access memory (SDRAM) has a plurality of memory cell arrays including a plurality of bit line pairs with each bit line connected to a plurality of memory cells, a plurality of sense amplifiers with each sense amplifier connected to a bit line pair of each memory cell array through a bank select switch, and a plurality of data line pairs. A plurality of pass gates includes a first pair of pass gates connecting a sense amplifier output of a bit line pair to a first data line pair, and a second pair of pass gates connecting the sense amplifier output of a bit line pair to a second data line pair, whereby each bit line pair is connectable through a sense amplifier to first and second data line pairs. In operation, the first data line pair and the second data line pair are toggled alternately in connection to the bit line pairs by alternating column select line signals (CSLA, CSLB).