Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes scanning a first memory region for bit errors; in response to detecting one or more bit errors in the first memory region, incrementing a counter associated with the first memory region based on the number of bit errors detected; comparing a total number of bit errors against a threshold, wherein the total number of bit errors is identified from the first counter; and, if the total number of bit errors exceeds the threshold, restricting access to the first memory region by mapping an address corresponding to the first memory region to a second memory region.

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes scanning a first memory region for bit errors; in response to detecting one or more bit errors in the first memory region, incrementing a counter associated with the first memory region based on the number of bit errors detected; comparing a total number of bit errors against a threshold, wherein the total number of bit errors is identified from the first counter; and, if the total number of bit errors exceeds the threshold, restricting access to the first memory region by mapping an address corresponding to the first memory region to a second memory region.

Abstract: A content addressable memory (CAM) comprising a plurality of CAM cells, each including a static read/write memory (RWM) cell and an EXCLUSIVE OR (XOR) gate which couples a sense line to a ground line only if the logic state of the operand bit stored in the RWM cell does not match the logic state of an operand bit presented to the CAM cell. By arranging a selected subset of the CAM cells so that the XOR gates thereof act upon a first portion of either the sense line or the ground line while the balance of the CAM cells are arranged so that the XOR gates thereof act upon a second portion of that same line, a single coupler interposed between the first and second portions can be selectively disabled by a mask signal to simultaneously mask all of the bits stored in the subset of CAM cells during the matching operation of the CAM. If appropriate, the mask signal may comprise the bit stored in a particular one of the CAM cells.