Patents by Inventor Teruaki Kanzaki
Teruaki Kanzaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10361683Abstract: An object of the present invention is to reduce burden on a program for changing an operation mode of an internal circuit in accordance with an internal clock frequency without mounting a large-scale circuit in an LSI in which setting of the frequency of an internal clock can be dynamically changed. In an LSI including an internal clock generation circuit generating an internal clock from a clock source in accordance with a parameter supplied, a register storing frequency information of the clock source, a register storing the parameter, and an internal circuit having a plurality of operation modes, a table circuit controlling the operation mode of the internal circuit in association with the frequency information and the parameter supplied from the registers is provided.Type: GrantFiled: June 11, 2018Date of Patent: July 23, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Teruaki Kanzaki
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Publication number: 20180294800Abstract: An object of the present invention is to reduce burden on a program for changing an operation mode of an internal circuit in accordance with an internal clock frequency without mounting a large-scale circuit in an LSI in which setting of the frequency of an internal clock can be dynamically changed. In an LSI including an internal clock generation circuit generating an internal clock from a clock source in accordance with a parameter supplied, a register storing frequency information of the clock source, a register storing the parameter, and an internal circuit having a plurality of operation modes, a table circuit controlling the operation mode of the internal circuit in association with the frequency information and the parameter supplied from the registers is provided.Type: ApplicationFiled: June 11, 2018Publication date: October 11, 2018Applicant: Renesas Electronics CorporationInventor: Teruaki KANZAKI
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Patent number: 10020799Abstract: An object of the present invention is to reduce burden on a program for changing an operation mode of an internal circuit in accordance with an internal clock frequency without mounting a large-scale circuit in an LSI in which setting of the frequency of an internal clock can be dynamically changed. In an LSI including an internal clock generation circuit generating an internal clock from a clock source in accordance with a parameter supplied, a register storing frequency information of the clock source, a register storing the parameter, and an internal circuit having a plurality of operation modes, a table circuit controlling the operation mode of the internal circuit in association with the frequency information and the parameter supplied from the registers is provided.Type: GrantFiled: March 30, 2017Date of Patent: July 10, 2018Assignee: Renesas Electronics CorporationInventor: Teruaki Kanzaki
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Publication number: 20170324399Abstract: An object of the present invention is to reduce burden on a program for changing an operation mode of an internal circuit in accordance with an internal clock frequency without mounting a large-scale circuit in an LSI in which setting of the frequency of an internal clock can be dynamically changed. In an LSI including an internal clock generation circuit generating an internal clock from a clock source in accordance with a parameter supplied, a register storing frequency information of the clock source, a register storing the parameter, and an internal circuit having a plurality of operation modes, a table circuit controlling the operation mode of the internal circuit in association with the frequency information and the parameter supplied from the registers is provided.Type: ApplicationFiled: March 30, 2017Publication date: November 9, 2017Applicant: Renesas Electronics CorporationInventor: Teruaki KANZAKI
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Patent number: 9627298Abstract: To enable a semiconductor device excellent in usability to be provided. A semiconductor device has a main surface surrounded by a plurality of sides, a semiconductor chip having a plurality of electrode pads arranged over the main surface, and a plurality of leads coupled to the electrode pads by way of wires respectively. The electrode pads include a plurality of first electrode pads supplied with a plurality of bits temporally in parallel. The first electrode pads include second and third electrode pads. A fourth electrode pad different from the first electrode pads is arranged between the second and third electrode pads.Type: GrantFiled: November 12, 2015Date of Patent: April 18, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Teruaki Kanzaki
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Publication number: 20160225698Abstract: To enable a semiconductor device excellent in usability to be provided. A semiconductor device has a main surface surrounded by a plurality of sides, a semiconductor chip having a plurality of electrode pads arranged over the main surface, and a plurality of leads coupled to the electrode pads by way of wires respectively. The electrode pads include a plurality of first electrode pads supplied with a plurality of bits temporally in parallel. The first electrode pads include second and third electrode pads. A fourth electrode pad different from the first electrode pads is arranged between the second and third electrode pads.Type: ApplicationFiled: November 12, 2015Publication date: August 4, 2016Inventor: Teruaki KANZAKI
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Patent number: 8178981Abstract: The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.Type: GrantFiled: March 2, 2010Date of Patent: May 15, 2012Assignee: Renesas Electronics CorporationInventors: Teruaki Kanzaki, Yoshinori Deguchi, Kazunobu Miki
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Patent number: 8067961Abstract: In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.Type: GrantFiled: December 9, 2009Date of Patent: November 29, 2011Assignee: Renesas Electronics CorporationInventor: Teruaki Kanzaki
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Publication number: 20100155960Abstract: The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.Type: ApplicationFiled: March 2, 2010Publication date: June 24, 2010Applicant: Renesas Technology CorporationInventors: Teruaki KANZAKI, Yoshinori Deguchi, Kazunobu Miki
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Publication number: 20100109745Abstract: In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.Type: ApplicationFiled: December 9, 2009Publication date: May 6, 2010Applicant: Renesas Technology Corp.Inventor: Teruaki Kanzaki
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Patent number: 7701063Abstract: The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.Type: GrantFiled: February 22, 2005Date of Patent: April 20, 2010Assignee: Renesas Technology Corp.Inventors: Teruaki Kanzaki, Yoshinori Deguchi, Kazunobu Miki
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Patent number: 7656201Abstract: When a first signal is switched from an L level to an H level and a second signal is switched from an H level to an L level, and a first constant current source cannot follow the switching immediately thereafter and has not yet been switched, a first node remains at an H level, so an output node remains at an L level. In such state, a second node having been connected to a third node of an H level before the switching becomes connected to the first node of an H level by the switching. At the same time, the output part of an inverter is switched from an H level to an L level, causing the second node to be switched from an H level to an L level as well via a capacitor. At this time, the potential of the first node is reduced to become equal to the second node, to make a transition to an L level.Type: GrantFiled: September 7, 2006Date of Patent: February 2, 2010Assignee: Renesas Technology Corp.Inventor: Teruaki Kanzaki
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Patent number: 7652505Abstract: In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.Type: GrantFiled: August 21, 2008Date of Patent: January 26, 2010Assignee: Renesas Technology Corp.Inventor: Teruaki Kanzaki
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Publication number: 20090002026Abstract: In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.Type: ApplicationFiled: August 21, 2008Publication date: January 1, 2009Applicant: Renesas Technology Corp.Inventor: Teruaki Kanzaki
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Patent number: 7432740Abstract: In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.Type: GrantFiled: September 21, 2005Date of Patent: October 7, 2008Assignee: Renesas Technology Corp.Inventor: Teruaki Kanzaki
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Publication number: 20070182001Abstract: The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.Type: ApplicationFiled: February 22, 2005Publication date: August 9, 2007Applicant: RENESAS TECHNOLOGY CORP.Inventors: Teruaki Kanzaki, Yoshinori Deguchi, Kazunobu Miki
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Publication number: 20070057705Abstract: When a first signal is switched from an L level to an H level and a second signal is switched from an H level to an L level, and a first constant current source cannot follow the switching immediately thereafter and has not yet been switched, a first node remains at an H level, so an output node remains at an L level. In such state, a second node having been connected to a third node of an H level before the switching becomes connected to the first node of an H level by the switching. At the same time, the output part of an inverter is switched from an H level to an L level, causing the second node to be switched from an H level to an L level as well via a capacitor. At this time, the potential of the first node is reduced to become equal to the second node, to make a transition to an L level.Type: ApplicationFiled: September 7, 2006Publication date: March 15, 2007Applicant: Renesas Technology Corp.Inventor: Teruaki Kanzaki
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Publication number: 20060061386Abstract: In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.Type: ApplicationFiled: September 21, 2005Publication date: March 23, 2006Applicant: Renesas Technology Corp.Inventor: Teruaki Kanzaki
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Patent number: 6996704Abstract: A branching source address in an absolute address representation and a branching destination address in a relative address representation are captured from a CPU so that the branching source address and the branching destination address are output tot he trace bus.Type: GrantFiled: August 13, 2003Date of Patent: February 7, 2006Assignee: Renesas Technology Corp.Inventor: Teruaki Kanzaki
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Patent number: 6839869Abstract: A trace control circuit includes a branch event generation circuit 1 having an address abbreviation information generation circuit 8 for detecting a portion in which a branch-source address and a branch-destination address are overlapped with each other from the upper-bit side of the address data thereof and generating branch-destination address abbreviation information on the basis of the result of the detection, and a trace data abbreviation circuit 5 for performing abbreviation of one part of trace data in accordance with the branch-destination address abbreviation information and outputting the partly abbreviated trace data, whereby the number of data packets of the trace data can be reduced to speed up the output operation of the trace data, and the ability to output trace data in real time can be thereby improved greatly.Type: GrantFiled: May 8, 2001Date of Patent: January 4, 2005Assignee: Renesas Technology Corp.Inventors: Yoshifumi Doi, Teruaki Kanzaki