Patents by Inventor Teruaki KUMAZAWA

Teruaki KUMAZAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240038711
    Abstract: A semiconductor device includes a semiconductor substrate and a metal layer disposed on a surface of the semiconductor substrate. The metal layer includes a first metal layer and a second metal layer. The second metal layer covers a surface of the first metal layer and has a higher solder wettability than the first metal layer. The second metal layer is exposed on a main surface of the metal layer. The first metal layer is exposed on a side surface of the metal layer. The metal layer has a protruding portion on the main surface. The protruding portion extends to make one round along an outer peripheral edge of the main surface.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 1, 2024
    Inventors: TERUAKI KUMAZAWA, MASASHI UECHA, YUJI NAGUMO, MASARU OKUDA, MASATAKE NAGAYA, MITSURU KITAICHI, AKIRA MORI, NAOYA KIYAMA, MASAKAZU TAKEDA
  • Patent number: 11881407
    Abstract: A method of manufacturing a chip formation wafer includes: forming an epitaxial film on a first main surface of a silicon carbide wafer to provide a processed wafer having one side adjacent to the epitaxial film and the other side; irradiating a laser beam into the processed wafer from the other side of the processed wafer so as to form an altered layer along a surface direction of the processed wafer; and separating the processed wafer with the altered layer as a boundary into a chip formation wafer having the one side of the processed wafer and a recycle wafer having the other side of the processed wafer. The processed wafer has a beveling portion at an outer edge portion of the processed wafer, and an area of the other side is larger than an area of the one side in the beveling portion.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 23, 2024
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation, DISCO Corporation
    Inventors: Masatake Nagaya, Teruaki Kumazawa, Yuji Nagumo, Kazuya Hirata, Asahi Nomoto
  • Publication number: 20230197519
    Abstract: In a manufacturing method of a semiconductor device, a semiconductor wafer that is made of a semiconductor material harder than silicon and has a first surface and a second surface opposite to each other is prepared, a roughened layer is formed by grinding the second surface of the semiconductor wafer, a blade is pressed against the roughened layer to form a vertical crack in a surface layer of the semiconductor wafer, the roughened layer is removed after the vertical crack is formed, a rear surface electrode is formed on a rear surface of the semiconductor wafer on which the vertical crack is formed, and after the rear surface electrode is formed, the first surface of the semiconductor wafer is pressed and the semiconductor wafer is cleaved into multiple pieces with the vertical crack as a starting point.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 22, 2023
    Inventors: YUJI NAGUMO, MASASHI UECHA, HIROKI TSUMA, TERUAKI KUMAZAWA
  • Publication number: 20230178497
    Abstract: A semiconductor device includes a semiconductor substrate, an end region, and an active region. The end region is located above the semiconductor substrate, has a frame shape, and has been brought into contact with a blade in a scribing process. The active region is surrounded by the end region and is configured to serve as a path of a main current. The end region has a stress relaxation film on an outermost surface of the end region.
    Type: Application
    Filed: November 15, 2022
    Publication date: June 8, 2023
    Inventors: Masashi UECHA, Yuji NAGUMO, Hiroki TSUMA, Teruaki KUMAZAWA
  • Publication number: 20230154987
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor layer and a side silicide layer. The silicon carbide semiconductor layer includes a silicon carbide single crystal and has a main surface, a rear surface opposite to the main surface, and a side surface connecting the main surface and the rear surface and formed by a cleavage plane. The silicon carbide semiconductor layer further includes a modified layer. The modified layer forms a part of the side surface located close to the rear surface and has an atomic arrangement structure of silicon carbide different from an atomic arrangement structure of the silicon carbide single crystal. The side silicide layer includes a metal silicide that is a compound of a metal element and silicon. The side silicide layer is disposed on the side surface of the silicon carbide semiconductor layer and is adjacent to the modified layer.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 18, 2023
    Inventors: HIROKI TSUMA, YUJI NAGUMO, MASASHI UECHA, TERUAKI KUMAZAWA
  • Patent number: 11387372
    Abstract: A semiconductor device includes; a schottky diode; a semiconductor substrate that includes a first surface and a second surface opposite to the first surface; a schottky electrode that is placed on the first surface and schottky-contacts to the semiconductor substrate; a first electrode placed on the schottky electrode; and a second electrode that is placed on the second surface and is connected to the semiconductor substrate. The schottky electrode is made of a metal material that is a columnar crystal; and a content of carbon on the schottky electrode is less than 6×1019 cm?3 in at least a part of an area of the schottky electrode.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: July 12, 2022
    Assignee: DENSO CORPORATION
    Inventors: Kouji Eguchi, Teruaki Kumazawa, Yusuke Yamashita
  • Publication number: 20220130675
    Abstract: A method of manufacturing a chip formation wafer includes: forming an epitaxial film on a first main surface of a silicon carbide wafer to provide a processed wafer having one side adjacent to the epitaxial film and the other side; irradiating a laser beam into the processed wafer from the other side of the processed wafer so as to form an altered layer along a surface direction of the processed wafer; and separating the processed wafer with the altered layer as a boundary into a chip formation wafer having the one side of the processed wafer and a recycle wafer having the other side of the processed wafer. The processed wafer has a beveling portion at an outer edge portion of the processed wafer, and an area of the other side is larger than an area of the one side in the beveling portion.
    Type: Application
    Filed: August 31, 2021
    Publication date: April 28, 2022
    Inventors: Masatake NAGAYA, Teruaki KUMAZAWA, Yuji NAGUMO, Kazuya HIRATA, Asahi NOMOTO
  • Publication number: 20210020788
    Abstract: A semiconductor device includes; a schottky diode; a semiconductor substrate that includes a first surface and a second surface opposite to the first surface; a schottky electrode that is placed on the first surface and schottky-contacts to the semiconductor substrate; a first electrode placed on the schottky electrode; and a second electrode that is placed on the second surface and is connected to the semiconductor substrate. The schottky electrode is made of a metal material that is a columnar crystal; and a content of carbon on the schottky electrode is less than 6×1019 cm?3 in at least a part of an area of the schottky electrode.
    Type: Application
    Filed: July 15, 2020
    Publication date: January 21, 2021
    Inventors: Kouji EGUCHI, Teruaki KUMAZAWA, Yusuke YAMASHITA
  • Patent number: 10177236
    Abstract: A method of manufacturing a semiconductor device includes: setting a plurality of main semiconductor wafers and a plurality of sub semiconductor wafers in a load lock chamber of an electrode forming equipment; repeating a wafer-transfer and electrode-formation process of transferring at least one of the main semiconductor wafers from the load lock chamber to the film formation chamber in a state where the load lock chamber and the film formation chamber are decompressed and then forming a surface electrode on a surface of the at least one main semiconductor wafer transferred in the film formation chamber; removing the main semiconductor wafers on which the surface electrodes have been formed and the sub semiconductor wafers from the electrode forming equipment without forming an electrode on the sub semiconductor wafers by the electrode forming equipment; and making the surface electrodes Schottky-contact the main semiconductor wafers.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: January 8, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Teruaki Kumazawa, Narumasa Soejima, Yuichi Takeuchi
  • Publication number: 20180286974
    Abstract: A provided method of manufacturing a semiconductor device includes formation of an interlayer insulating. The interlayer insulating film includes first and second insulating layers. The first insulating layer covers an upper surface of each of the gate electrodes. The second insulating layer is located on the first insulating layer. A contact hole is provided in the interlayer insulating film at a position between the trenches. Then the interlayer insulating film is heated at a temperature lower than the softening temperature of the first insulating layer and higher than the softening temperature of the second insulating layer so as to make a surface of the second insulating layer into a curved surface so that surfaces of end portions of the second insulating layer are sloping from the corresponding contact holes so as to be displaced upward toward a center of the corresponding trench.
    Type: Application
    Filed: September 16, 2016
    Publication date: October 4, 2018
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Teruaki KUMAZAWA, Shinichiro MIYAHARA, Sachiko AOI
  • Publication number: 20180145144
    Abstract: A method of manufacturing a semiconductor device includes: setting a plurality of main semiconductor wafers and a plurality of sub semiconductor wafers in a load lock chamber of an electrode forming equipment; repeating a wafer-transfer and electrode-formation process of transferring at least one of the main semiconductor wafers from the load lock chamber to the film formation chamber in a state where the load lock chamber and the film formation chamber are decompressed and then forming a surface electrode on a surface of the at least one main semiconductor wafer transferred in the film formation chamber; removing the main semiconductor wafers on which the surface electrodes have been formed and the sub semiconductor wafers from the electrode forming equipment without forming an electrode on the sub semiconductor wafers by the electrode forming equipment; and making the surface electrodes Schottky-contact the main semiconductor wafers.
    Type: Application
    Filed: October 16, 2017
    Publication date: May 24, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Teruaki KUMAZAWA, Narumasa SOEJIMA, Yuichi TAKEUCHI