Patents by Inventor Teruaki Nishinaka

Teruaki Nishinaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220412728
    Abstract: A bead appearance inspection device includes an input unit configured to enter input data related to a welding bead of a workpiece produced by welding, and a determination unit configured to perform an inspection determination related to a shape of the welding bead based on the input data. The determination unit determines which of a range of a value indicating a non-defective product zone, a range of a value indicating a gray zone, and a range of a value indicating a defective product zone a value obtained from the input data belongs to. The range of the value indicating the gray zone is between the range of the value indicating the non-defective product zone and the range of the value indicating the defective product zone.
    Type: Application
    Filed: September 1, 2022
    Publication date: December 29, 2022
    Inventors: Katsuaki OKUMA, Kazuyuki NAKASHIMA, Teruaki NISHINAKA
  • Patent number: 9439336
    Abstract: In a component mounting system, a portable operation terminal is wirelessly connectable to mounting machines. The portable operation terminal includes: a processing portion which displays a screen allowing a worker to select one of the mounting machines to be connected to the portable operation terminal; and a terminal-side connection processing portion which issues a connection request to the selected mounting machine and which connects the portable operation terminal to the mounting machine upon reception of an acknowledgement from the mounting machine. The mounting machine includes: an equipment-side connection processing portion which connects the mounting machine to the portable operation terminal in response to the connection request, and a notification unit which notifies the worker of the fact that the mounting machine has been connected to the portable operation terminal, directly by at least one of sound and light.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: September 6, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takahiro Yokomae, Nobuya Matsuo, Teruaki Nishinaka
  • Patent number: 9332681
    Abstract: In a case where a solder amount of a solder portion printed on an electrode does not meet a reference amount, solder is additionally applied to a center position of the electrode by a control section. With respect to a component mounting position to which the solder is not additionally applied, correction from a component mounting position of a substrate to a corrected mounting position is performed and an electronic component is mounted at the corrected mounting position. The electronic component corresponding to another component mounting position with the solder additionally applied thereto is mounted at the design component mounting position in the positioned substrate.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: May 3, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masayuki Mantani, Teruaki Nishinaka
  • Publication number: 20150289426
    Abstract: In a case where a solder amount of a solder portion printed on an electrode does not meet a reference amount, solder is additionally applied to a center position of the electrode by a control section. With respect to a component mounting position to which the solder is not additionally applied, correction from a component mounting position of a substrate to a corrected mounting position is performed and an electronic component is mounted at the corrected mounting position. The electronic component corresponding to another component mounting position with the solder additionally applied thereto is mounted at the design component mounting position in the positioned substrate.
    Type: Application
    Filed: November 15, 2013
    Publication date: October 8, 2015
    Inventors: Masayuki Mantani, Teruaki Nishinaka
  • Publication number: 20150135524
    Abstract: In a component mounting system, a portable operation terminal is wirelessly connectable to mounting machines. The portable operation terminal includes: a processing portion which displays a screen allowing a worker to select one of the mounting machines to be connected to the portable operation terminal; and a terminal-side connection processing portion which issues a connection request to the selected mounting machine and which connects the portable operation terminal to the mounting machine upon reception of an acknowledgement from the mounting machine. The mounting machine includes: an equipment-side connection processing portion which connects the mounting machine to the portable operation terminal in response to the connection request, and a notification unit which notifies the worker of the fact that the mounting machine has been connected to the portable operation terminal, directly by at least one of sound and light.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 21, 2015
    Inventors: Takahiro YOKOMAE, Nobuya MATSUO, Teruaki NISHINAKA
  • Patent number: 8293652
    Abstract: To provide a substrate processing method and a semiconductor chip manufacturing method that enable low-cost formation of a mask for etching using plasma etching. During formation of a mask used in plasma dicing for separating a semiconductor wafer 1 into discrete semiconductor chips 1e by means of etching using plasma processing, there is adopted a method including printing a lyophobic liquid in an area on a rear surface 1b that is to be an objective of etching, thereby forming a lyophobic pattern made up of lyophobic films 3; supplying a low viscosity resin 4a and a high viscosity resin 4b, in this sequence, to the rear surface 1b on which the lyophobic pattern is formed, thereby forming a resin film 4 that is thicker than the lyophobic films 3 in an area where the lyophobic films 3 are not present; and curing the resin film 4, to thus form a mask 4* that covers an area except for the area to be etched.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: October 23, 2012
    Assignee: Panasonic Corporation
    Inventors: Kiyoshi Arita, Teruaki Nishinaka
  • Publication number: 20120015522
    Abstract: To provide a substrate processing method and a semiconductor chip manufacturing method that enable low-cost formation of a mask for etching using plasma etching. During formation of a mask used in plasma dicing for separating a semiconductor wafer 1 into discrete semiconductor chips 1e by means of etching using plasma processing, there is adopted a method including printing a lyophobic liquid in an area on a rear surface 1b that is to be an objective of etching, thereby forming a lyophobic pattern made up of lyophobic films 3; supplying a low viscosity resin 4a and a high viscosity resin 4b, in this sequence, to the rear surface 1b on which the lyophobic pattern is formed, thereby forming a resin film 4 that is thicker than the lyophobic films 3 in an area where the lyophobic films 3 are not present; and curing the resin film 4, to thus form a mask 4* that covers an area except for the area to be etched.
    Type: Application
    Filed: April 9, 2010
    Publication date: January 19, 2012
    Applicant: Panasonic Corporation
    Inventors: Kiyoshi Arita, Teruaki Nishinaka
  • Patent number: 7989803
    Abstract: In a semiconductor wafer that has semiconductor devices arranged in a plurality of device-formation-regions and a TEG placed in dividing regions that define the device-formation-regions, a TEG-placement portion is arranged in the dividing regions partially expanded in width, and the TEG is placed in the TEG-placement portion. Additionally, a protective sheet is stuck to the semiconductor wafer, then plasma etching is performed, and the TEG is removed in a state where it remains in the dividing region and stuck to the protective sheet together with the protective sheet by peeling off the protective sheet, thereby the device-formation-regions are divided into individual pieces, and the semiconductor chips are manufactured.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: August 2, 2011
    Assignee: Panasonic Corporation
    Inventors: Kiyoshi Arita, Teruaki Nishinaka
  • Patent number: 7797822
    Abstract: An electronic component mounting method of thermo-compressing and mounting electronic components onto a plurality of unit boards segmented in a multi-piece board which avoids the occurrence of adverse thermal influences on the thermosetting bonding material which is placed on the unit boards before mounting the electronic components. The thermo-compression tool used in the method is removably fitted on a thermo-compression head in an electronic component mounting apparatus; the thermo-compression tool includes a base member and a suck-up member which is smaller than a lower surface of the base member and which is fixed on the lower surface of the base member at a position displaced from a center thereof.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Tadahiko Sakai, Hideki Eifuku, Teruaki Nishinaka
  • Patent number: 7629228
    Abstract: On a mask placement-side surface of a semiconductor wafer in which a plurality of semiconductor devices are formed, a mask is placed, while dicing lines for dicing the semiconductor wafer into the respective separate semiconductor devices are defined and a surface of a flawed semiconductor device among the respective semiconductor devices is partially exposed, and then plasma etching is applied to the mask placement-side surface of the semiconductor wafer so as to dice the semiconductor wafer into the respective semiconductor devices along the defined dicing lines, and an exposed portion of the flawed semiconductor device is removed so as to form a removed portion as a flawed semiconductor device distinguishing mark.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: December 8, 2009
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Haji, Kiyoshi Arita, Teruaki Nishinaka
  • Publication number: 20090126188
    Abstract: A thermo-compression tool removably fitted on a thermo-compression head in an electronic component mounting apparatus includes a base member which is removably fitted on a head-bottom face of the thermo-compression head and in which heating by heat transfer for thermo-compression is performed through the head-bottom face of the head, and a suck-up member having a suck-up surface which is formed so as to be smaller than a lower surface of the base member in correspondence to a size of the electronic component and by which the electronic component is sucked up and held, the suck-up member being fixed on the lower surface of the base member at a position displaced from a center thereof.
    Type: Application
    Filed: June 16, 2006
    Publication date: May 21, 2009
    Inventors: Tadahiko Sakai, Hideki Eifuku, Teruaki Nishinaka
  • Patent number: 7488668
    Abstract: With use of a length-dimension of a second-line-segment of a unit-device-formation-region as an arrangement interval, a plurality of parallel lines are disposed in a device-formation-effective-region on a wafer so as to form a plurality of parallel-line-partition-regions, the unit-device-formation-regions are arranged in each of the parallel-line-partition-regions independently of and separately from other parallel-line-partition-regions so that the acquisition number of the unit-device-formation-regions is maximized, and an arrangement of the respective unit-device-formation-regions in the respective parallel-line-partition-regions is determined as an arrangement of the entire device-formation-effective-region.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: February 10, 2009
    Assignee: Panasonic Corporation
    Inventors: Kiyoshi Arita, Hiroshi Haji, Kazuhiro Noda, Akira Nakagawa, Teruaki Nishinaka
  • Publication number: 20080128694
    Abstract: In a semiconductor wafer that has semiconductor devices arranged in a plurality of device-formation-regions and a TEG placed in dividing regions that define the device-formation-regions, a TEG-placement portion is arranged in the dividing regions partially expanded in width, and the TEG is placed in the TEG-placement portion. And, a protective sheet is stuck to the semiconductor wafer, then plasma etching is performed, and the TEG in a state where it remains in the dividing region and stuck to the protective sheet is removed together with the protective sheet by peeling off the protective sheet, thereby the device-formation-regions are divided into individual pieces, and the semiconductor chips are manufactured.
    Type: Application
    Filed: January 10, 2006
    Publication date: June 5, 2008
    Inventors: Kiyoshi Arita, Teruaki Nishinaka
  • Patent number: 7107672
    Abstract: A plurality of flexible printed circuit boards are held on a transfer carrier, which is formed by a base plate and a resin layer formed on an upper surface of the base plate. Reference pins are positioned at reference pin openings of the carrier base plate and reference holes of the flexible printed circuit boards are positioned at the reference pins in order to adhere the board to the carrier resin layer. Electronic parts are mounted on the flexible printed circuit board by bonding the electronic parts to bonding portions of the flexible printed circuit board.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: September 19, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuto Onitsuka, Teruaki Nishinaka
  • Publication number: 20060024924
    Abstract: On a mask placement-side surface of a semiconductor wafer in which a plurality of semiconductor devices are formed, a mask is placed, while dicing lines for dicing the semiconductor wafer into the respective separate semiconductor devices are defined and a surface of a flawed semiconductor device among the respective semiconductor devices is partially exposed, and then plasma etching is applied to the mask placement-side surface of the semiconductor wafer so as to dice the semiconductor wafer into the respective semiconductor devices along the defined dicing lines, and an exposed portion of the flawed semiconductor device is removed so as to form a removed portion as a flawed semiconductor device distinguishing mark.
    Type: Application
    Filed: August 1, 2005
    Publication date: February 2, 2006
    Inventors: Hiroshi Haji, Kiyoshi Arita, Teruaki Nishinaka
  • Publication number: 20060019416
    Abstract: With use of a length-dimension of a second-line-segment of a unit-device-formation-region as an arrangement interval, a plurality of parallel lines are disposed in a device-formation-effective-region on a wafer so as to form a plurality of parallel-line-partition-regions, the unit-device-formation-regions are arranged in each of the parallel-line-partition-regions independently of and separately from other parallel-line-partition-regions so that the acquisition number of the unit-device-formation-regions is maximized, and an arrangement of the respective unit-device-formation-regions in the respective parallel-line-partition-regions is determined as an arrangement of the entire device-formation-effective-region.
    Type: Application
    Filed: July 19, 2005
    Publication date: January 26, 2006
    Inventors: Kiyoshi Arita, Hiroshi Haji, Kazuhiro Noda, Akira Nakagawa, Teruaki Nishinaka
  • Publication number: 20040027811
    Abstract: To provide a transfer carrier for a flexible printed circuit board and an electronic parts mounting method on a flexible printed circuit board which can cope with different mounting methods by using the same transfer carrier.
    Type: Application
    Filed: August 6, 2003
    Publication date: February 12, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuto Onitsuka, Teruaki Nishinaka
  • Patent number: 6013899
    Abstract: A pickup head 11 has a lower surface with absorbing holes 9 for picking up a plurality of soldering balls 1 from a soldering ball reservoir 15 by suction force of vacuum. Pickup head 11 mounts these soldering balls 1 on electrodes 5 formed on substrate 4 placed on a conveyor 8. Then, soldering balls 1 are transported below a camera 21. Camera 21 monitors the upper surface of substrate 4 to check whether each of electrodes 5 mounts a soldering ball 1. An absorbing head 31 mounts a supplemental soldering ball 1 on a faulty electrode 5 which lacks a soldering ball 1 to be mounted thereon when this faulty electrode 5 is detected by camera 21. After all of electrodes 5 mount soldering balls 1, substrate 4 is sent by conveyor 8 to a furnace 40 where each soldering ball 1 is heated and melted to form soldering bumps 1' on electrodes 5.
    Type: Grant
    Filed: September 24, 1997
    Date of Patent: January 11, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeru Eguchi, Teruaki Nishinaka
  • Patent number: 5894984
    Abstract: An improved structure of an electronic part with solder bumps is provided. The electronic part includes, for example, an IC chip and a board. The solder bumps are disposed on the bottom surface of the board and have a melting point greater than a thermal deformation temperature of the board. With this arrangement, if the curved board is bonded to a substrate in a soldering process, the solder bumps are solidified at a higher temperature than the thermal deformation temperature of the board during a cooling process, thereby preventing the curved board which has been straightened once above the thermal deformation temperature from being returned to its original shape. Several modifications are disclosed.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: April 20, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadahiko Sakai, Shoji Sakemi, Teruaki Nishinaka
  • Patent number: 5779958
    Abstract: An electronic device packaging apparatus using molding techniques is provided. This packaging apparatus includes an upper die, a lower die, and a resin injection mechanism. The lower die is designed to mate with the upper die, and includes a cavity block which has an upper block surface and a lower block surface. The upper block surface has formed therein a mold cavity for packaging an electronic device placed between the upper and lower dies with a resin material. The lower block surface has formed therein a groove communicating with the mold cavity. The resin injection mechanism is operable to inject a melted resin material into the mold cavity of the cavity block through the groove formed in the lower block surface of the cavity block.
    Type: Grant
    Filed: January 14, 1997
    Date of Patent: July 14, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Syoujirou Nishihara, Teruaki Nishinaka