Patents by Inventor Teruaki Sakata

Teruaki Sakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7752527
    Abstract: A microcontroller in which an increase in hardware is suppressed and data correction capability for software error of RAM can be improved is provided. A microcontroller which performs processing according to a program includes a CPU and a RAM for storing data processed by the CPU, wherein multiplexed regions are defined in the RAM, and when these regions are accessed, an access to an address outputted by the CPU and a copy access to an address obtained by adding or subtracting a certain value to or from the address outputted by the CPU are performed. By this means, the same data can be stored in a plurality of regions and the reliability can be improved.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: July 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Hiromichi Yamada, Teppei Hirotsu, Teruaki Sakata, Takeshi Kataoka, Shunichi Iwata
  • Publication number: 20090249271
    Abstract: Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.
    Type: Application
    Filed: February 19, 2009
    Publication date: October 1, 2009
    Inventors: Hiromichi Yamada, Nobuyasu Kanekawa, Teruaki Sakata
  • Publication number: 20090024777
    Abstract: There is provided a technique which reduces an average processing time of low-priority accesses with suppressing an average delay increase of a high-priority access processing even in a case where high-priority access request and a low-request access request are simultaneously generated to a shared access processing unit and high-priority accesses are continuously generated. And, there is provided an access arbitration equipment comprising: an issued access request retention unit; a first interval determination circuit; and a second interval determination circuit. In a case where the first interval determination circuit determines that an interval is generated between an issued access processing and a most prior access processing and a second interval determination circuit determines that no interval is generated between the issued access processing and a second-prior access request, the priority order of the most prior access request and the second-prior access request is changed.
    Type: Application
    Filed: June 5, 2008
    Publication date: January 22, 2009
    Inventors: Teppei Hirotsu, Kotaro Shimamura, Teruaki Sakata, Noboru Sugihara
  • Publication number: 20080046603
    Abstract: A control device diagnoses the operation of a bus arbiter that mediates bus usage requests output by multiple devices in the control device to satisfy both responsiveness and safety. A diagnostic module, implemented as an external diagnostic module, monitors signals related to the arbiter mediation and, if an abnormality caused by a signal sticking condition or an abnormality in a mediation control unit is detected, stops data transfer safely to prevent safety data from being output incorrectly.
    Type: Application
    Filed: June 28, 2007
    Publication date: February 21, 2008
    Inventors: Eiji Kobayashi, Akira Bandou, Masamitsu Kobayashi, Masahiro Shiraishi, Akihiro Onozuka, Takashi Umehara, Shin Kokura, Masakazu Ishikawa, Yasuyuki Furuta, Satoru Funaki, Yuusuke Seki, Tatsuyuki Ootani, Teruaki Sakata, Kotaro Shimamura
  • Publication number: 20070180317
    Abstract: This method is an error correction method such that, when an error is detected in a CPU with pipeline struct, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.
    Type: Application
    Filed: January 16, 2007
    Publication date: August 2, 2007
    Inventors: Teppei HIROTSU, Hiromichi Yamada, Teruaki Sakata, Kesami Hagiwara
  • Publication number: 20070124559
    Abstract: A microcontroller in which an increase in hardware is suppressed and data correction capability for software error of RAM can be improved is provided. A microcontroller which performs processing according to a program includes a CPU and a RAM for storing data processed by the CPU, wherein multiplexed regions are defined in the RAM, and when these regions are accessed, an access to an address outputted by the CPU and a copy access to an address obtained by adding or subtracting a certain value to or from the address outputted by the CPU are performed. By this means, the same data can be stored in a plurality of regions and the reliability can be improved.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 31, 2007
    Inventors: Hiromichi Yamada, Teppai Hirotsu, Teruaki Sakata, Takeshi Kataoka, Shunichi Iwata
  • Patent number: 6896042
    Abstract: The present invention relates to the structure of a pipe plate unit for heat exchangers which may be employed in condensers, etc. that is used in thermoelectric and nuclear power plants. The object of this invention is to provide a structure for heat exchanger pipe plate units which reduces the number of construction steps and the labor costs for replacement of the pipe plate units, and which results in a pipe plate unit for heat exchangers after the replacement process that maintains a good seal for the fluids and which is adequately strong.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: May 24, 2005
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Koichi Inoue, Teruaki Sakata, Satoshi Hiraoka, Hiroji Nakamae
  • Publication number: 20050027921
    Abstract: A prefetch address calculation unit detects a branch instruction and a data access instruction to be reliably executed from a series of instruction included in an entry that is stored in a buffer at 1 cycle and outputs a prefetch request of its target address to a control unit. Then, decoding types of the series of instruction that is included in the entry, and setting it at an instruction type flag, the prefetch address calculation unit masks the output of the instruction type flag that has been executed by using an address signal of the instruction that is being executing presently and outputs a location of the instruction for issuing a prefetch request. By a signal from a control unit, the prefetch address calculation unit clears an instruction type flag corresponding to the instruction that issued the prefetch request.
    Type: Application
    Filed: May 11, 2004
    Publication date: February 3, 2005
    Inventors: Teppei Hirotsu, Kotaro Shimamura, Noboru Sugihara, Yasuhiro Nakatsuka, Teruaki Sakata
  • Publication number: 20030164232
    Abstract: The present invention relates to the structure of a pipe plate unit for heat exchangers which may be employed in condensers, etc. that is used in thermoelectric and nuclear power plants. The object of this invention is to provide a structure for heat exchanger pipe plate units which reduces the number of construction steps and the labor costs for replacement of the pipe plate units, and which results in a pipe plate unit for heat exchangers after the replacement process that maintains a good seal for the fluids and which is adequately strong.
    Type: Application
    Filed: February 10, 2003
    Publication date: September 4, 2003
    Applicant: MITSUBISHI HEAVY INDUSTRIES LTD.
    Inventors: Koichi Inoue, Teruaki Sakata, Satoshi Hiraoka, Hiroji Nakamae
  • Patent number: 5794448
    Abstract: A fuel heating apparatus for a gas turbineis provided in which contact of high temperature air and fuel at the time of fuel leakage is prevented so that safety is ensured. The apparatus includes a turbine cooling air cooler of the air cooling type for cooling turbine cooling air and a fuel heater connected to the exhaust side of the turbine cooling air cooler for heating the fuel by the refrigerant air. The turbine cooling air cooler and the fuel heater 4, respectively, form a separate unit so that contact of high temperature air and fuel at the time of fuel leakage is prevented.
    Type: Grant
    Filed: April 5, 1996
    Date of Patent: August 18, 1998
    Assignee: Mitsubishi Jukogyo Kabushiki Kaisha
    Inventors: Masanori Fujioka, Teruaki Sakata, Carmelo Osmena Dilao